From 63d038ee6377f76af0799abeb5780ada7fbdb2fe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=D0=94=D0=BC=D0=B8=D1=82=D1=80=D0=B8=D0=B9=20=D0=94=D1=91?= =?UTF-8?q?=D0=BC=D0=B8=D0=BD?= Date: Wed, 22 Oct 2025 20:40:25 +0300 Subject: [PATCH] Initial commit --- .editorconfig | 17 + .gitea/workflows/actions.md | 4 + .gitea/workflows/push-branch.yaml | 56 + .gitea/workflows/push-release-tag.yaml | 73 + .gitignore | 12 + .vscode/c_cpp_properties.json | 41 + .vscode/extensions.json | 18 + .vscode/launch.json | 106 + .vscode/settings.json | 114 + .vscode/tasks.json | 125 + Makefile | 237 + README.md | 3 + libs/Buffer.h | 73 + libs/Can.h | 288 + libs/CanFwInterface.cpp | 99 + libs/CanFwInterface.h | 291 + libs/CanSources.cpp | 56 + libs/CommonTypes.h | 335 + libs/IO.h | 329 + libs/LinBus.h | 212 + libs/LinFrame.h | 81 + libs/ModelName.h | 9 + libs/Periodic.h | 166 + libs/Settings.cpp | 67 + libs/Settings.h | 267 + libs/SettingsTable.h | 687 + libs/SysTimer.h | 83 + libs/Utils.h | 73 + libs/WeakFunc.cpp | 40 + src/CAN_FW.h | 17 + src/CAN_Inputs.h | 22 + src/CAN_Outputs.h | 5 + src/SettingsCANTable.h | 98 + src/immo/Immo.h | 16 + src/immo/immo.cpp | 30 + src/immo/immo.md | 1 + src/source/SourcePath.h | 11 + sys/M1_CAN_FW.ld | 147 + sys/M3_CAN_FW.ld | 147 + sys/STM32F107.svd | 42416 +++++++++++++++++ sys/STM32F446.svd | 56913 +++++++++++++++++++++++ sys/allowed_signers.sh | 70 + sys/changelog.sh | 38 + sys/export.bat | 4 + sys/export.ps1 | 3 + sys/export.sh | 17 + sys/export.zsh | 4 + sys/hex2fw.sh | 184 + sys/info/JLink_drivers_install.png | Bin 0 -> 6191 bytes sys/info/install.md | 108 + sys/install.sh | 103 + sys/srecord/libgcrypt-20.dll | Bin 0 -> 1294922 bytes sys/srecord/libgpg-error-0.dll | Bin 0 -> 207210 bytes sys/srecord/srec_cat.exe | Bin 0 -> 1539098 bytes sys/version.sh | 53 + sys/zdotdir/.gitignore | 3 + sys/zdotdir/.zshrc | 6 + 57 files changed, 104378 insertions(+) create mode 100644 .editorconfig create mode 100644 .gitea/workflows/actions.md create mode 100644 .gitea/workflows/push-branch.yaml create mode 100644 .gitea/workflows/push-release-tag.yaml create mode 100644 .gitignore create mode 100644 .vscode/c_cpp_properties.json create mode 100644 .vscode/extensions.json create mode 100644 .vscode/launch.json create mode 100644 .vscode/settings.json create mode 100644 .vscode/tasks.json create mode 100644 Makefile create mode 100644 README.md create mode 100644 libs/Buffer.h create mode 100644 libs/Can.h create mode 100644 libs/CanFwInterface.cpp create mode 100644 libs/CanFwInterface.h create mode 100644 libs/CanSources.cpp create mode 100644 libs/CommonTypes.h create mode 100644 libs/IO.h create mode 100644 libs/LinBus.h create mode 100644 libs/LinFrame.h create mode 100644 libs/ModelName.h create mode 100644 libs/Periodic.h create mode 100644 libs/Settings.cpp create mode 100644 libs/Settings.h create mode 100644 libs/SettingsTable.h create mode 100644 libs/SysTimer.h create mode 100644 libs/Utils.h create mode 100644 libs/WeakFunc.cpp create mode 100644 src/CAN_FW.h create mode 100644 src/CAN_Inputs.h create mode 100644 src/CAN_Outputs.h create mode 100644 src/SettingsCANTable.h create mode 100644 src/immo/Immo.h create mode 100644 src/immo/immo.cpp create mode 100644 src/immo/immo.md create mode 100644 src/source/SourcePath.h create mode 100644 sys/M1_CAN_FW.ld create mode 100644 sys/M3_CAN_FW.ld create mode 100644 sys/STM32F107.svd create mode 100644 sys/STM32F446.svd create mode 100755 sys/allowed_signers.sh create mode 100755 sys/changelog.sh create mode 100644 sys/export.bat create mode 100644 sys/export.ps1 create mode 100644 sys/export.sh create mode 100644 sys/export.zsh create mode 100755 sys/hex2fw.sh create mode 100644 sys/info/JLink_drivers_install.png create mode 100644 sys/info/install.md create mode 100755 sys/install.sh create mode 100644 sys/srecord/libgcrypt-20.dll create mode 100644 sys/srecord/libgpg-error-0.dll create mode 100644 sys/srecord/srec_cat.exe create mode 100755 sys/version.sh create mode 100644 sys/zdotdir/.gitignore create mode 100644 sys/zdotdir/.zshrc diff --git a/.editorconfig b/.editorconfig new file mode 100644 index 0000000..aad9ed4 --- /dev/null +++ b/.editorconfig @@ -0,0 +1,17 @@ +# EditorConfig is awesome: https://EditorConfig.org + +# top-most EditorConfig file +root = true + +[*] +charset = utf-8 +trim_trailing_whitespace = true +insert_final_newline = false + +[*.{h,cpp,json,sh,bat,ps1,ld}] +indent_style = tab +indent_size = 4 + +[*.py] +indent_style = space +indent_size = 2 diff --git a/.gitea/workflows/actions.md b/.gitea/workflows/actions.md new file mode 100644 index 0000000..bc1719c --- /dev/null +++ b/.gitea/workflows/actions.md @@ -0,0 +1,4 @@ +## Actions + +* `push-branch.yaml` - Тестовая сборка при пуше веток. +* `push-release-tag.yaml` - Сборка релиза и загрузка черновика со всеми файлами при пуше тэга релиза. diff --git a/.gitea/workflows/push-branch.yaml b/.gitea/workflows/push-branch.yaml new file mode 100644 index 0000000..94505b5 --- /dev/null +++ b/.gitea/workflows/push-branch.yaml @@ -0,0 +1,56 @@ +# https://docs.gitea.com/usage/actions/overview +# https://github.com/marketplace?type=actions +# https://gitea.com/actions +# https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions +name: Push Branch +on: + push: + branches: + - '**' + +jobs: + Build_Test: + name: Build Test + runs-on: ubuntu-latest + steps: + + # https://github.com/actions/checkout + - name: Checkout repository + uses: actions/checkout@v4 + with: + fetch-depth: 0 + fetch-tags: true + + - name: Dev Tools Cache + uses: actions/cache@v3 + with: + path: | + ~/.xpack-dev-tools + /usr/bin/xxd + /usr/bin/srec_cat + /lib/x86_64-linux-gnu/libsrecord.so.0.0.0 + /lib/x86_64-linux-gnu/libsrecord.so.0 + key: ${{ runner.os }}-xpack-dev-tools-xxd-srecord + + - name: Dev Tools install + run: sys/install.sh + + - name: Build M2 Debug + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M2 debug + + - name: Build M2 Release + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M2 release + + - name: Build M3 Debug + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M3 debug + + - name: Build M3 Release + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M3 release + + - name: Changelog + if: success() || failure() + run: sys/changelog.sh; cat CHANGELOG.md diff --git a/.gitea/workflows/push-release-tag.yaml b/.gitea/workflows/push-release-tag.yaml new file mode 100644 index 0000000..abfeb47 --- /dev/null +++ b/.gitea/workflows/push-release-tag.yaml @@ -0,0 +1,73 @@ +# https://docs.gitea.com/usage/actions/overview +# https://github.com/marketplace?type=actions +# https://gitea.com/actions +# https://docs.github.com/en/actions/using-workflows/workflow-syntax-for-github-actions +name: Push Release Tag +on: + push: + tags: + - 'v*' + - '*_v*' + +jobs: + Build_and_draft_Release_tag: + name: Build Release and Draft + runs-on: ubuntu-latest + steps: + + # https://github.com/actions/checkout + - name: Checkout repository + uses: actions/checkout@v4 + with: + fetch-depth: 0 + fetch-tags: true + + - name: Dev Tools Cache + uses: actions/cache@v3 + with: + path: | + ~/.xpack-dev-tools + /usr/bin/xxd + /usr/bin/srec_cat + /lib/x86_64-linux-gnu/libsrecord.so.0.0.0 + /lib/x86_64-linux-gnu/libsrecord.so.0 + key: ${{ runner.os }}-xpack-dev-tools-xxd-srecord + + - name: Dev Tools install + run: sys/install.sh + + - name: Build M2 Release + id: M2 + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M2 release + + - name: Build M3 Release + id: M3 + if: success() || failure() + run: . sys/export.sh; make -e MODEL=M3 release + + - name: Changelog + if: success() || failure() + run: sys/changelog.sh; cat CHANGELOG.md + + # https://github.com/actions/setup-node + - name: Node setup + # https://docs.github.com/en/actions/writing-workflows/choosing-what-your-workflow-does/accessing-contextual-information-about-workflow-runs#steps-context + if: ( ${{ success() }} || ${{ failure() }} ) && ( ${{ steps.M2.outcome }} == 'success' || ${{ steps.M3.outcome }} == 'success' ) + uses: actions/setup-node@v4 + with: + node-version: 18 + + # https://github.com/akkuman/gitea-release-action + - name: Upload Draft Release + if: ( ${{ success() }} || ${{ failure() }} ) && ( ${{ steps.M2.outcome }} == 'success' || ${{ steps.M3.outcome }} == 'success' ) + uses: akkuman/gitea-release-action@v1 + with: + token: '${{secrets.ACTION_TOKEN}}' + body: 'Описание релиза' + body_path: 'CHANGELOG.md' + draft: true + prerelease: true + files: |- + build/M2_Release/*.fw + build/M3_Release/*.fw diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b42d278 --- /dev/null +++ b/.gitignore @@ -0,0 +1,12 @@ +/build +/CHANGELOG.md +/libs/Version.h + +/.vscode/* +!/.vscode/c_cpp_properties.json +!/.vscode/extensions.json +!/.vscode/launch.json +!/.vscode/settings.json +!/.vscode/tasks.json + +sys/__pycache__/ \ No newline at end of file diff --git a/.vscode/c_cpp_properties.json b/.vscode/c_cpp_properties.json new file mode 100644 index 0000000..d0a53a3 --- /dev/null +++ b/.vscode/c_cpp_properties.json @@ -0,0 +1,41 @@ +{ + "configurations": [ + { + "name": "M2", + "intelliSenseMode": "gcc-arm", + "cStandard": "c17", + "cppStandard": "c++17", + "includePath": [ + "libs", + "src" + ], + "defines": [ + "DEBUG", + "STM32F10X_CL", + "HSE_VALUE=16000000", + "CAN_FIRMWARE=1", + "MOBICAR_1_2=1" + ], + "compilerPath": "${userHome}/.xpack-dev-tools/xpack-arm-none-eabi-gcc-12.3.1-1.2/bin/arm-none-eabi-gcc" + }, + { + "name": "M3", + "intelliSenseMode": "gcc-arm", + "cStandard": "c17", + "cppStandard": "c++17", + "includePath": [ + "libs", + "src" + ], + "defines": [ + "DEBUG", + "STM32F10X_CL", + "HSE_VALUE=16000000", + "CAN_FIRMWARE=1", + "MOBICAR_3=1" + ], + "compilerPath": "${userHome}/.xpack-dev-tools/xpack-arm-none-eabi-gcc-12.3.1-1.2/bin/arm-none-eabi-gcc" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/.vscode/extensions.json b/.vscode/extensions.json new file mode 100644 index 0000000..f061133 --- /dev/null +++ b/.vscode/extensions.json @@ -0,0 +1,18 @@ +{ + "recommendations": [ + /* mandatory extensions */ + "ms-vscode.cpptools", // C/C++ support + "marus25.cortex-debug", // Cortex-Debug + /* handy extensions (optional) */ + "spencerwmiles.vscode-task-buttons",// Run tasks using statusbar buttons + "mhutchie.git-graph", // Git Graph + "pkief.material-icon-theme", // Icons + "ZixuanWang.linkerscript", // Linker Script files syntax + "trond-snekvik.gnu-mapfiles", // Linker Map files syntax + "keroc.hex-fmt", // Intel Hex files syntax + "ms-vscode.hexeditor", // Hex editor for binary files + "dan-c-underwood.arm", // ARM Assembly files syntax + "EditorConfig.EditorConfig", // editorconfig + "YuTengjing.open-in-external-app", // Open files in external app + ] +} \ No newline at end of file diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 0000000..75a48bd --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,106 @@ +{ + "configurations": [ + { + "name": "Debug M2", + "request": "launch", + "preLaunchTask": "Build M2 Debug", + "executable": "./build/M2_Debug/CAN_FW.elf", + "cwd": "${workspaceRoot}", + "showDevDebugOutput": "parsed", + "type": "cortex-debug", + // J-Link config // + "servertype": "jlink", + "serverArgs": ["-speed", "4000"], + "windows": { + "serverpath": "C:/Program Files/SEGGER/JLink/JLinkGDBServerCL.exe" + }, + "osx": { + "serverpath": "/Applications/SEGGER/JLink/JLinkGDBServer" + }, + "device": "STM32F105VC", + "svdFile": "sys/STM32F107.svd", + "swoConfig": + { + "enabled": true, + "cpuFrequency": 36000000, + "swoFrequency": 12000000, + "source": "probe", + "decoders": + [ + { + "label": "ITM", + "type": "console", + "port": 0, + "showOnStartup": true, + "encoding": "ascii", + } + ] + }, + // "rttConfig": { + // "enabled": true, + // "address": "auto", + // "decoders": [ + // { + // "label": "RTT Log", + // "port": 0, + // "type": "console", + // "noprompt": true, + // } + // ] + // }, + // Other // + "internalConsoleOptions": "neverOpen" + }, + { + "name": "Debug M3", + "request": "launch", + "preLaunchTask": "Build M3 Debug", + "executable": "./build/M3_Debug/CAN_FW.elf", + "cwd": "${workspaceRoot}", + "showDevDebugOutput": "parsed", + "type": "cortex-debug", + // J-Link config // + "servertype": "jlink", + "serverArgs": ["-speed", "4000"], + "windows": { + "serverpath": "C:/Program Files/SEGGER/JLink/JLinkGDBServerCL.exe" + }, + "osx": { + "serverpath": "/Applications/SEGGER/JLink/JLinkGDBServer" + }, + "device": "STM32F446ZE", + "svdFile": "sys/STM32F446.svd", + "swoConfig": + { + "enabled": true, + "cpuFrequency": 36000000, + "swoFrequency": 12000000, + "source": "probe", + "decoders": + [ + { + "label": "ITM", + "type": "console", + "port": 0, + "showOnStartup": true, + "encoding": "ascii" + } + ] + }, + // "rttConfig": { + // "enabled": true, + // "address": "auto", + // "decoders": [ + // { + // "label": "RTT Log", + // "port": 0, + // "type": "console", + // "noprompt": true, + // } + // ] + // }, + // Other // + "internalConsoleOptions": "neverOpen" + } + ] +} \ No newline at end of file diff --git a/.vscode/settings.json b/.vscode/settings.json new file mode 100644 index 0000000..c840ab6 --- /dev/null +++ b/.vscode/settings.json @@ -0,0 +1,114 @@ +{ + // Terminal profiles: + "terminal.integrated.profiles.windows": { + "Git Bash": { + "source": "Git Bash", + // "icon": "tools", + "color": "terminal.ansiGreen", + "overrideName": false, + "env": {}, + "args": ["--init-file", "sys/export.sh"] + }, + "Command Prompt": { + "path": "C:/Windows/System32/cmd.exe", + // "icon": "tools", + "color": "terminal.ansiGreen", + "overrideName": false, + "env": {}, + "args": ["/k call sys/export.bat"] + }, + "PowerShell": { + "source": "PowerShell", + // "icon": "tools", + "color": "terminal.ansiGreen", + "overrideName": false, + "env": {}, + "args": ["-noexit", "-file", "sys/export.ps1"] + } + }, + + "terminal.integrated.defaultProfile.linux": "Build bash", + "terminal.integrated.profiles.linux": { + "Build bash": { + "path": "bash", + "icon": "terminal-bash", + "color": "terminal.ansiGreen", + "overrideName": true, + "env": {}, + "args": ["--init-file", "sys/export.sh"] + }, + "Build zsh": { + "path": "zsh", + "icon": "terminal", + "color": "terminal.ansiGreen", + "overrideName": true, + "env": {"ZDOTDIR": "sys/zdotdir"}, + "args": [] + } + }, + + "terminal.integrated.defaultProfile.osx": "Build zsh", + "terminal.integrated.profiles.osx": { + "Build bash": { + "path": "bash", + "icon": "terminal-bash", + "color": "terminal.ansiGreen", + "overrideName": true, + "env": {}, + "args": ["--init-file", "sys/export.sh"] + }, + "Build zsh": { + "path": "zsh", + "icon": "terminal", + "color": "terminal.ansiGreen", + "overrideName": true, + "env": {"ZDOTDIR": "sys/zdotdir"}, + "args": [] + } + }, + + // Cortex-Debug + "cortex-debug.armToolchainPath": "${userHome}/.xpack-dev-tools/xpack-arm-none-eabi-gcc-12.3.1-1.2/bin", + + // C/C++ + "C_Cpp.autoAddFileAssociations": false, + + // Task Buttons extention + "VsCodeTaskButtons.showCounter": false, + "VsCodeTaskButtons.tasks": [ + { + "label": "$(tools) M2 Release", + "alignment": "left", + "task": "Build M2 Release" + }, + { + "label": "$(tools) M3 Release", + "alignment": "left", + "task": "Build M3 Release" + }, + { + "label": "$(tools) M2 Debug", + "alignment": "left", + "task": "Build M2 Debug" + }, + { + "label": "$(tools) M3 Debug", + "alignment": "left", + "task": "Build M3 Debug" + }, + { + "label": "$(tools) Clean", + "alignment": "left", + "task": "Clean" + }, + ], + "workbench.editorAssociations": { + "*.o": "hexEditor.hexedit", + "*.elf": "hexEditor.hexedit", + "*.bin": "hexEditor.hexedit", + "*.fw": "hexEditor.hexedit" + }, + "search.exclude": { + "build/**": true + } +} diff --git a/.vscode/tasks.json b/.vscode/tasks.json new file mode 100644 index 0000000..8f8d456 --- /dev/null +++ b/.vscode/tasks.json @@ -0,0 +1,125 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "Build M2 Release", + "type": "process", + "command": "bash", + "args": ["-c", ". sys/export.sh && make -e MODEL=M2 release"], + "windows": { + "command": "C:/Windows/System32/cmd.exe", + "args": ["/c call sys/export.bat && make -e MODEL=M2 release"] + }, + "osx": { + "type": "shell" + }, + "icon": {"id": "tools", "color": "terminal.ansiGreen"}, + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Build M3 Release", + "type": "process", + "command": "bash", + "args": ["-c", ". sys/export.sh && make -e MODEL=M3 release"], + "windows": { + "command": "C:/Windows/System32/cmd.exe", + "args": ["/c call sys/export.bat && make -e MODEL=M3 release"] + }, + "osx": { + "type": "shell" + }, + "icon": {"id": "tools", "color": "terminal.ansiGreen"}, + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Build M2 Debug", + "type": "process", + "command": "bash", + "args": ["-c", ". sys/export.sh && make -e MODEL=M2 debug"], + "windows": { + "command": "C:/Windows/System32/cmd.exe", + "args": ["/c call sys/export.bat && make -e MODEL=M2 debug"] + }, + "osx": { + "type": "shell" + }, + "icon": {"id": "tools", "color": "terminal.ansiGreen"}, + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Build M3 Debug", + "type": "process", + "command": "bash", + "args": ["-c", ". sys/export.sh && make -e MODEL=M3 debug"], + "windows": { + "command": "C:/Windows/System32/cmd.exe", + "args": ["/c call sys/export.bat && make -e MODEL=M3 debug"] + }, + "osx": { + "type": "shell" + }, + "icon": {"id": "tools", "color": "terminal.ansiGreen"}, + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + }, + { + "label": "Clean", + "type": "process", + "command": "bash", + "args": ["-c", ". sys/export.sh && rm -rf build"], + "windows": { + "command": "C:/Windows/System32/cmd.exe", + "args": ["/c call sys/export.bat && rm -rf build"] + }, + "osx": { + "type": "shell" + }, + "icon": {"id": "tools", "color": "terminal.ansiGreen"}, + "options": { + "cwd": "${workspaceRoot}" + }, + "group": { + "kind": "build", + "isDefault": true + }, + "problemMatcher": [ + "$gcc" + ] + } + ] +} \ No newline at end of file diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..8b84b1b --- /dev/null +++ b/Makefile @@ -0,0 +1,237 @@ +# Use install.sh for Build Tools installation +# Use . export.sh for PATH settings + +# https://stackoverflow.com/questions/1612278/pre-build-step-in-makefile + +TARGET = CAN_FW + +DEBUG = 1 + +OPT = -Og + +ifeq ($(DEBUG), 1) +BUILD_DIR = build/$(MODEL)_Debug +else +BUILD_DIR = build/$(MODEL)_Release +endif + +####################################### +# SOURCES +####################################### + +C_SOURCES = \ + + +CPP_SOURCES = \ +$(wildcard libs/*.cpp) \ +$(wildcard src/*.cpp) \ +$(wildcard src/immo/*.cpp) + + +ASM_SOURCES = \ + + +####################################### +# INCLUES +####################################### + +# AS includes +AS_INCLUDES = + +# C includes +C_INCLUDES = \ +-Ilibs \ +-Isrc + +####################################### +# OTHER MAKE VARIABLES +####################################### + +CXX = arm-none-eabi-g++ +CC = arm-none-eabi-gcc +AS = arm-none-eabi-gcc -x assembler-with-cpp +CP = arm-none-eabi-objcopy +SZ = arm-none-eabi-size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary -S + +# mcu +MCU = -mcpu=cortex-m3 -mthumb + +# AS defines +AS_DEFS = + +# C defines +C_DEFS = -DSTM32F10X_CL -DHSE_VALUE=16000000 -DCAN_FIRMWARE=1 + +# CXX defines +CXX_DEFS = -DSTM32F10X_CL -DHSE_VALUE=16000000 -DCAN_FIRMWARE=1 + +ifeq ($(MODEL),M2) +C_DEFS += -DMOBICAR_1_2=1 +CXX_DEFS += -DMOBICAR_1_2=1 +endif + +ifeq ($(MODEL),M3) +C_DEFS += -DMOBICAR_3=1 +CXX_DEFS += -DMOBICAR_3=1 +endif + +# compile gcc flags +ASFLAGS = $(MCU) $(AS_DEFS) $(AS_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections +CFLAGS = $(MCU) $(C_DEFS) $(C_INCLUDES) $(OPT) -Wall -fdata-sections -ffunction-sections + +CXXFLAGS = $(MCU) $(CXX_DEFS) $(C_INCLUDES) $(OPT) +CXXFLAGS += -Wall# All warnings +CXXFLAGS += -fmessage-length=0# Number of lines for error messages +CXXFLAGS += -fsigned-char# Default char is signed +CXXFLAGS += -fdata-sections -ffunction-sections# Place each function or data item into its own section (use garbage collector --gc-sections in linker) +CXXFLAGS += -ffreestanding# Freestanding environment (without standard library) +CXXFLAGS += -Wuninitialized# Uninitialized variables warning +CXXFLAGS += -Wpointer-arith# Warning for arithmetic operations with 'void *' +CXXFLAGS += -Wshadow# Warning if a local var shadows another one +CXXFLAGS += -Wlogical-op# Warn about suspicious uses of logical operators in expressions +CXXFLAGS += -Waggregate-return# Warn if any functions that return structures or unions are defined or called +CXXFLAGS += -Wfloat-equal# Warn if floating-point values are used in equality comparisons +CXXFLAGS += -std=gnu++11# C++ standart +CXXFLAGS += -fabi-version=0# Fix ABI version +CXXFLAGS += -fno-exceptions# Disable the generation of code needed to support C++ exceptions +CXXFLAGS += -fno-rtti# Disable C++ runtime +CXXFLAGS += -fno-use-cxa-atexit# Do not use standard library for calling destructors +CXXFLAGS += -fno-threadsafe-statics# Do not emit the extra code to use the routines specified in the C++ ABI for thread-safe initialization of local statics + + +ifeq ($(DEBUG), 1) +CFLAGS += -g -gdwarf -ggdb +CXXFLAGS += -g -gdwarf -ggdb +C_DEFS += -DDEBUG +CXX_DEFS += -DDEBUG +endif + +# Generate dependency information +CFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" +CXXFLAGS += -MMD -MP -MF"$(@:%.o=%.d)" + +####################################### +# LDFLAGS +####################################### +# link script +ifeq ($(MODEL),M2) +LDSCRIPT = sys/M1_CAN_FW.ld +endif +ifeq ($(MODEL),M3) +LDSCRIPT = sys/M3_CAN_FW.ld +endif + +LDFLAGS = $(MCU) +LDFLAGS += -Wl,--gc-sections# Dead code removal (linker garbage collector) +LDFLAGS += -Wl,--print-memory-usage# Print FLASH/RAM memory table +LDFLAGS += -T$(LDSCRIPT)# Linker script +# LDFLAGS += -Wl,-Map=$(BUILD_DIR)/$(TARGET).map# MAP file +LDFLAGS += -nostartfiles# Do not use startup code before the main() +LDFLAGS += -nodefaultlibs# Do not use default libs +LDFLAGS += -nostdlib# Do not use std lib +LDFLAGS += -Wl,--no-warn-rwx-segment# Remove RWX warning + + +####################################### +# build the application +####################################### +# list of cpp program objects +OBJECTS = $(addprefix $(BUILD_DIR)/, $(CPP_SOURCES:.cpp=.cpp.o)) + +# list of C objects +OBJECTS += $(addprefix $(BUILD_DIR)/, $(C_SOURCES:.c=.c.o)) + +# list of ASM program objects +UPPER_CASE_ASM_SOURCES = $(filter %.S, $(ASM_SOURCES)) +LOWER_CASE_ASM_SOURCES = $(filter %.s, $(ASM_SOURCES)) + +OBJECTS += $(addprefix $(BUILD_DIR)/, $(UPPER_CASE_ASM_SOURCES:.S=.S.o)) +OBJECTS += $(addprefix $(BUILD_DIR)/, $(LOWER_CASE_ASM_SOURCES:.s=.s.o)) + +# default action +.DEFAULT_GOAL := all +all: + @echo Use MODEL variable with debug/release target: + @echo make -e MODEL=M2 debug + @echo make -e MODEL=M2 release + @echo make -e MODEL=M3 debug + @echo make -e MODEL=M3 release + +# Colors +NC =\e[0m +RED =\e[0;31m +GREEN =\e[0;32m +BLUE =\e[0;36m + +.SECONDEXPANSION: + +ERROR_HANDLER = && printf "$(GREEN)OK$(NC)\n" || (printf "$(RED)ERROR$(NC)\n"; exit 1) + +$(BUILD_DIR)/%.cpp.o: %.cpp Makefile | $$(@D)/ + @printf "compile $(BLUE)$<$(NC) " + @$(CXX) -E -c $(CXXFLAGS) $< -o $@ || (printf "$(RED)ERROR$(NC)\n"; exit 1) + @iconv -f UTF-8 -t CP1251 $@ > $@.i + @$(CXX) -c $(CXXFLAGS) $@.i -o $@ $(ERROR_HANDLER) + +$(BUILD_DIR)/%.c.o: %.c Makefile | $$(@D)/ + @printf "compile $(BLUE)$<$(NC) " + @$(CC) -c $(CFLAGS) $< -o $@ $(ERROR_HANDLER) + +$(BUILD_DIR)/%.s.o: %.s Makefile | $$(@D)/ + @printf "compile $(BLUE)$<$(NC) " + @$(AS) -c $(CFLAGS) $< -o $@ $(ERROR_HANDLER) + +$(BUILD_DIR)/%.S.o: %.S Makefile | $$(@D)/ + @printf "compile $(BLUE)$<$(NC) " + @$(AS) -c $(CFLAGS) $< -o $@ $(ERROR_HANDLER) + +$(BUILD_DIR)/$(TARGET).elf: $(OBJECTS) Makefile + @printf "linking $(BLUE)$@$(NC)\n" + @$(CXX) $(OBJECTS) $(LDFLAGS) -o $@ || (printf "$(RED)linker ERROR$(NC)\n"; exit 1) +# $(SZ) $@ + +# https://www.cmcrossroads.com/article/making-directories-gnu-make +%/: + @mkdir -p $@ + +$(BUILD_DIR)/%.hex: $(BUILD_DIR)/%.elf + @printf "generate $(BLUE)$@$(NC) " + @$(HEX) $< $@ $(ERROR_HANDLER) + @sys/hex2fw.sh $@ || exit 1 + +ifeq ($(DEBUG), 1) +STARTMSG = Building $(MODEL) Debug +else +STARTMSG = Building $(MODEL) Release +endif + +build_app: + @printf "$(GREEN)-----------------------$(NC)\n" + @printf "$(GREEN) $(STARTMSG)$(NC)\n" + @printf "$(GREEN)-----------------------$(NC)\n" + @sys/version.sh; +# @sys/changelog.sh; + @make -j --no-print-directory --output-sync $(BUILD_DIR)/$(TARGET).hex + @printf "$(GREEN)-----------------------$(NC)\n" + +clean: + @rm -rf $(BUILD_DIR) + +debug: + @make clean --no-print-directory + @make build_app --no-print-directory + +release: + @make clean --no-print-directory -e DEBUG=0 + @make build_app --no-print-directory -e OPT=-Os DEBUG=0 + +printvars: + @echo "MODEL: $(MODEL)" + @echo "C_DEFS: $(C_DEFS)" + @echo "CXX_DEFS: $(CXX_DEFS)" + +-include $(OBJECTS:.o=.d) + +# *** EOF *** \ No newline at end of file diff --git a/README.md b/README.md new file mode 100644 index 0000000..ad84c6a --- /dev/null +++ b/README.md @@ -0,0 +1,3 @@ +## Шаблон проекта CAN-прошивки + +[Подготовка к работе](sys/info/install.md) \ No newline at end of file diff --git a/libs/Buffer.h b/libs/Buffer.h new file mode 100644 index 0000000..a8cb9c2 --- /dev/null +++ b/libs/Buffer.h @@ -0,0 +1,73 @@ +/* + * Buffer.h + * + * Created on: 03 апр. 2015 г. + * Author: esaulenko + */ + +#ifndef _BUFFER_H_ +#define _BUFFER_H_ + +#include + + +// простейший кольцевой буфер. +// проверки при добавлении/извлечении данных отсутствуют, надо проверять отдельно!! + +template +class CircularBuffer +{ +private: + Type buff[Size]; + volatile uint32_t putIdx; + volatile uint32_t getIdx; + +public: + CircularBuffer() + { + Flush (); + } + + void Put (const Type & data) + { + buff[putIdx] = data; + putIdx = (putIdx + 1) % Size; + } + + Type Get () + { + Type data = buff[getIdx]; + getIdx = (getIdx + 1) % Size; + return data; + } + + Type & View () + { + return buff[getIdx]; + } + + uint32_t Avail () const + { + int32_t avail = putIdx - getIdx; + if (avail < 0) avail += Size; + return avail; + } + + uint32_t Free () const + { + int32_t free = getIdx - putIdx - 1; + if (free < 0) free += Size; + return free; + } + + void Flush () + { + putIdx = getIdx = 0; + } + + +}; + + + +#endif /* _BUFFER_H_ */ diff --git a/libs/Can.h b/libs/Can.h new file mode 100644 index 0000000..7eef4d8 --- /dev/null +++ b/libs/Can.h @@ -0,0 +1,288 @@ +/* + * Can.h + * + * Created on: 01 июня 2015 г. + * Author: esaulenko + */ + +#ifndef DRIVERS_CAN_CAN_H_ +#define DRIVERS_CAN_CAN_H_ + + +#include +#include "CommonTypes.h" +#ifndef CAN_FIRMWARE + #include "SysTimer.h" + #include "Buffer.h" + #include "scmRTOS.h" +#endif + + + + +struct TCanPkt +{ + uint32_t id; + uint8_t data[8]; + uint8_t data_len; + + TCanPkt() { } + + TCanPkt (uint32_t pkt_id): + id(pkt_id) { } + + // принимает строку, заполняет данные пакета. Неуказанные данные заполняются нулями + template + inline void SetData (const char (&data_str)[N]) + { + int data_size = (N <= 8) ? (N - 1) : 8; + for (int i = 0; i < data_size; i++) + data[i] = data_str[i]; + for (int i = data_size; i < 8; i++) + data[i] = 0x00; + } + + inline void SetData (uint8_t A) + { data_len = 1; + data[0] = A; data[1] = 0; data[2] = 0; data[3] = 0; + data[4] = 0; data[5] = 0; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B) + { data_len = 2; + data[0] = A; data[1] = B; data[2] = 0; data[3] = 0; + data[4] = 0; data[5] = 0; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C) + { data_len = 3; + data[0] = A; data[1] = B; data[2] = C; data[3] = 0; + data[4] = 0; data[5] = 0; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C, uint8_t D) + { data_len = 4; + data[0] = A; data[1] = B; data[2] = C; data[3] = D; + data[4] = 0; data[5] = 0; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C, uint8_t D, uint8_t E) + { data_len = 5; + data[0] = A; data[1] = B; data[2] = C; data[3] = D; + data[4] = E; data[5] = 0; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C, uint8_t D, uint8_t E, uint8_t F) + { data_len = 6; + data[0] = A; data[1] = B; data[2] = C; data[3] = D; + data[4] = E; data[5] = F; data[6] = 0; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C, uint8_t D, uint8_t E, uint8_t F, uint8_t G) + { data_len = 7; + data[0] = A; data[1] = B; data[2] = C; data[3] = D; + data[4] = E; data[5] = F; data[6] = G; data[7] = 0; + } + inline void SetData (uint8_t A, uint8_t B, uint8_t C, uint8_t D, uint8_t E, uint8_t F, uint8_t G, uint8_t H) + { data_len = 8; + data[0] = A; data[1] = B; data[2] = C; data[3] = D; + data[4] = E; data[5] = F; data[6] = G; data[7] = H; + } + +}; + + +struct TCanInit +{ + uint32_t baudrate; // "сырое" значение регистра BTR, см. TCanBaudrate + uint8_t mode; // в наст. момент не используется. TODO Должно быть RO / RW + uint64_t filters[27]; // массив со значениями для пар регистров; заполняется Filters::xxx +}; + + + +class CCan +{ +public: + + enum TCanState : uint8_t + { + CanActive, + CanRxOnly, // внешний драйвер выключен + CanSleep, // внешний драйвер выключен, модуль в спящем режиме + + CanInitError = 0xFE, + CanBusOff = 0xFF, + }; + +/* TIME QUANTUM FREQUENCY: + Ftq = Ntq * Fbaud + where 8 <= Ntq <= 25, and Ntq - is integer! + + BAUD RATE PRESCALER: + BRP = (Fcan/Ftq)–1 + + INDIVIDUAL BIT TIME SEGMENTS: + (Bit Time) = (Sync Segment) + (Time Segment 1) + (Time Segment 2) + where + (Sync Segment) = 1*Tq (constant) + (Time Segment 2) ~= 30% of Nominal Bit Time = Ntq/3 + (Time Segment 2) > 1*Tq + (Time Segment 1) > 3*Tq + (Time Segment 1) > (Time Segment 2) + (Time Segment 1) <= (Time Segment 2)+8 + (Synchronous Jump Width) <= (Time Segment 2) + +Table of Parameters: +--------+-----------------------------------------------------+ +BRP@Fcan| Ntq | + 9MHz |25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10| 9| 8| +--------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +500.000 | | | | | | | | 0| | | | | | | | | 1| | +250.000 | | | | | | | | 1| | | | | | 2| | | 3| | +125.000 | | 2| | | | | | 3| | | | | | 5| | | 7| 8| +100.000 | | | | | | | | 4| | | 5| | | | | 8| 9| | + 83.333 | | | | | | | | 5| | | | | | 8| | |11| | + 50.000 | | | | | | 8| | 9| | |11| | |14| |17|19| | + 33.333 | | | | | | | |14| | |17| | | | |26|29| | + 20.000 |17| | | | | | |24| | |29| | | | |44|49| | + 15.000 |23|24| | | |29| | | | |39| | |49| |59| |74| + 10.000 |35| | | | |44| |49| | |59| | |74| |89|99| | +--------+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ +*/ +#define CAN_BTR(BRP,TSEG1,TSEG2,SJW) (((((((SJW)&0x03)<<4)|((TSEG2)&0x07))<<4)|((TSEG1)&0x0F))<<16)|((BRP)&0x3FF) + + // значения регистра BTR + enum TCanBaudrate { + CanBaudrate500 = CAN_BTR(0,10,5,3), + + CanBaudrate250 = CAN_BTR(1,10,5,3), + +// CanBaudrate125 = CAN_BTR(2,14,7,3), + CanBaudrate125 = CAN_BTR(3,10,5,3), + + CanBaudrate100 = CAN_BTR(4,10,5,3), + + CanBaudrate83 = CAN_BTR(5,10,5,3), + +// CanBaudrate50 = CAN_BTR(8,11,6,3), + CanBaudrate50 = CAN_BTR(9,10,5,3), + + CanBaudrate33 = CAN_BTR(14,10,5,3), + + CanBaudrate20 = CAN_BTR(17,15,7,3), +// CanBaudrate20 = CAN_BTR(24,10,5,3), + + CanBaudrate15 = CAN_BTR(23,15,7,3), +// CanBaudrate15 = CAN_BTR(24,14,7,3), +// CanBaudrate15 = CAN_BTR(29,11,6,3), + + CanBaudrate10 = CAN_BTR(35,15,7,3), +// CanBaudrate10 = CAN_BTR(44,11,6,3), +// CanBaudrate10 = CAN_BTR(49,10,5,3), + + }; + +#ifndef CAN_FIRMWARE + CCan (); + + uint32_t Init (TCanChannel aCh, const TCanInit * apInit); + + uint32_t Send (TCanChannel aCh, TCanPkt * apPkt, uint32_t aTimeout); + + void ReceivedIsr (TCanChannel aCh, TCanPkt * apPkt); + + uint32_t ProcessQueue (); + + uint32_t GetRcv (TCanChannel aCh, TCanPkt * apPkt); + + uint32_t GetRcvTimeout (TCanChannel aCh) + { return _rx_tmr[aCh].Value(); } + +#endif // CAN_FIRMWARE + + // объявление фильтров при инициализации + struct Filter { + // добавить пару идентификаторов для точного соответствия + static constexpr uint64_t List11 (uint16_t id1, uint16_t id2) + { + return ((uint64_t) (IdStd (id1) | 0x01) << 32) | + (uint64_t) (IdStd (id2) | 0x01); + } + static constexpr uint64_t List29 (uint32_t id1, uint32_t id2) + { + return ((uint64_t) (IdExt (id1) | 0x01) << 32) | + (uint64_t) (IdExt (id2) | 0x01); + } + + // добавить один идентификатор + static constexpr uint64_t List11 (uint16_t id1) + { + return ((uint64_t) (IdStd (id1) | 0x01) << 32) | + (uint64_t) (IdStd (id1) | 0x01); + } + static constexpr uint64_t List29 (uint32_t id1) + { + return ((uint64_t) (IdExt (id1) | 0x01) << 32) | + (uint64_t) (IdExt (id1) | 0x01); + } + + + // добавить один идентификатор с маской + static constexpr uint64_t Mask11 (uint16_t id, uint16_t mask) + { + return ((uint64_t) (IdStd (id)) << 32) | + (uint64_t) (IdStd (mask) | 0x01); + } + static constexpr uint64_t Mask29 (uint32_t id, uint32_t mask) + { + return ((uint64_t) (IdExt (id)) << 32) | + (uint64_t) (IdExt (mask) | 0x01); + } + + private: + // формирование ID для фильтров + static constexpr uint32_t IdStd (uint16_t id) + { return (id & 0x7FFul) << 21; } + static constexpr uint32_t IdExt (uint32_t id) + { return ((id & 0x1FFFFFFFul) << 3) | 0x04; } + }; + + + +#ifndef CAN_FIRMWARE +private: + + uint8_t sleep_en; + bool IsSleepEn (TCanChannel aCh) + { return sleep_en & aCh; } + + + // очередь пакетов на отправку - тот же TCanPkt, но с таймером + struct TCanPktTxInt: public TCanPkt { + uint32_t timeout; + TimerMs tmr; + }; + + typedef CircularBuffer TRxBuf; + typedef CircularBuffer TTxBuf; + + TRxBuf _rx_buf[2]; + TTxBuf _tx_buf[2]; + + uint32_t TxByTimeout (TCanChannel aCh); + + bool IsTxQueueEmpty (TCanChannel aCh); + + TCanState _state[2]; + + // Send() и обработка очереди вызываются из разных потоков, нужна защита + OS::TMutex can_mutex; + + // сбрасывается по приёму любого пакета + TimerMs _rx_tmr[2]; + +#endif // CAN_FIRMWARE +}; + + + +extern CCan gCan; + + + +#endif /* DRIVERS_CAN_CAN_H_ */ diff --git a/libs/CanFwInterface.cpp b/libs/CanFwInterface.cpp new file mode 100644 index 0000000..3bc1322 --- /dev/null +++ b/libs/CanFwInterface.cpp @@ -0,0 +1,99 @@ +/* + * CanFwInterface.cpp + * + * Created on: 13 мая 2015 г. + * Author: esaulenko + */ + +#include "ModelName.h" +#include "source/SourcePath.h" +#include SRC_HEADER +#include "CanFwInterface.h" +#include "Utils.h" +#include "Settings.h" +#include "Version.h" +#include + + + + +// заглушка для неиспользуемых функций +//void Empty (__attribute__((unused)) void * apCanFwMem) {}; +void Empty () {}; + + + + +// контрольная сумма, располагается линкером в самом конце прошивки +__attribute__ ((section(".CheckSum"))) +static const uint32_t CanChksum = CHKSUM_DEBUG; + + +// описание прошивки +const TCanFwInfo gCanFwInfo = +{ + (CAN_FW_VERSION << 24) | BUILD_DATE, // Version - Версия ПО + GIT_BUILD, // Хеш коммита в репозитории git + &CanChksum, // *pCRC32 - Адрес, где расположена CRC32 + 0, // reserved2 + M_NAME CAN_FW_DESCRIPTION "_" GIT_VERSION // TextInfo[64] - Текстовая информация +}; + + + +// структура с функциями CAN, которые вызываются из ядра +__attribute__ ((section(".entrance_vector"))) +TCanFunctions CanFuctTable = +{ + &gCanFwInfo, // pCanFwInfo + (uint8_t *) & CSettings::CanSettingsTable, // pSettingsTable + CSettings::CanSettingsName, // pSettingsNames + + Init, + PeriodicProcess, + + SettingChanged, + Empty, // Reserved6 + + InputChanged, + OutputChanged, + GuardEvent, + + Can1Received, + Can2Received, + + SequenceStart, + SequenceStop, + + Command, + + Lin1Received, + Lin2Received, + Lin1Transmitted, + Lin2Transmitted, +#if defined MOBICAR_1_2 + Empty, // Reserved19 + Empty, // Reserved20 +#elif defined MOBICAR_3 + Lin3Received, + Lin3Transmitted, +#endif + + Empty, // Reserved21 + Empty, // Reserved22 + Empty, // Reserved23 + Empty, // Reserved24 + Empty, // Reserved25 + Empty, // Reserved26 + Empty, // Reserved27 + Empty, // Reserved28 + Empty, // Reserved29 + Empty, // Reserved30 + Empty, // Reserved31 +}; + + +// проверка, что переменные влезают в соотв.область +static_assert (sizeof(TCanFwMem) <= gCanFwMemSize, "Превышен максимальный размер TCanFwMem"); + + diff --git a/libs/CanFwInterface.h b/libs/CanFwInterface.h new file mode 100644 index 0000000..205ca9b --- /dev/null +++ b/libs/CanFwInterface.h @@ -0,0 +1,291 @@ +/* + * CanFwInterface.h + * + * Created on: 13 мая 2015 г. + * Author: esaulenko + */ + +#ifndef CANFWINTERFACE_H_ +#define CANFWINTERFACE_H_ + +#include "CommonTypes.h" + +// размер области памяти под переменные CAN-прошивки +enum { gCanFwMemSize = 2048 }; + +// объявляем структуры заранее, чтобы не было взаимных ссылок +struct TCanPkt; + +union TLinInit; +struct TLinFrame; + +#if CAN_FIRMWARE + struct TCanFwMem; +#else // Core + typedef char TCanFwMem[gCanFwMemSize]; +#endif + +// команды ядра, которые может вызывать CAN-прошивка +enum TCoreCommands : uint8_t { + CoreCmdDisarm = 1, // команда снятия с охраны Параметр: b00CHASFL + // бит 0(L) - отпирать замки; + // бит 1(F) - мигать поворотниками; + // бит 2(S) - гудеть сиреной; + // бит 3(A) - если команда подана в режиме тревоги, прекратить ее, не снимая с охраны; + // бит 4(H) - режим Handsfree, позволяет сниматься с Охраны в любой момент начала Автозапуска и блокирует Перепостановку; + // бит 5(C) - выдавать сигналы управления функциями Комфорта. + CoreCmdArm = 2, // команда постановки на охрану Параметр: b00C00SFL + // бит 0(L) - запирать замки; + // бит 1(F) - мигать поворотниками; + // бит 2(S) - гудеть сиреной; + // бит 5(C) - выдавать сигналы управления функциями Комфорта. + CoreCmdTrunkOpened = 3, // команда оповещения Системы о том, что багажник открыт: b00000SF0 + //CoreCmdAlarm = 6, // не реализовано + CoreCmdDisableShockSens = 7, // Отключить реакцию на датчик Удара в течении <Параметр> времени в мсек + CoreCmdDisableDoorSens = 8, // Задержать реакцию на концевики дверей в течении <Параметр> времени в мсек + CoreCmdLauncherOn = 9, // команда оповещения Системы о включении внешнего запуска: <Параметр> - время ожидания запуска в сек + CoreCmdLauncherOff = 10, // команда оповещения Системы о выключении внешнего запуска: <Параметр> - время ожидания глушения или перезапуска в сек + CoreCmdDisableTrunkSens = 11, // Задержать реакцию на концевики багажника в течении <Параметр> времени в мсек + CoreCmdImmoLearnRes = 12, // Результат обучения иммобилайзера: 0 - успех, нужно запомнить VIN, 0x80 - успех, VIN не нужен, другое - ошибка + CoreCmdImmoLearnContinue = 13, // Управление обучением иммо: 1 - перезапуск таймаута; 2 - необходимо выключить зажигание; 3 - подать сигнал антенным модулем + CoreCmdStartStop = 14, // Управление запуском со штатного брелока (например, трехкратным нажатием на кнопку закрыть) + CoreCmdMenuResult = 15, // Результат выполнения команды из меню антенны: 0 - успех, 1 - ошибка +}; + +// Список команд предназначеных/определенных/известных CAN прошивке +enum TCanFwCommands : uint8_t { + ccNone = 0, // нет команды/не команда, либо команда неизвестна/неопределена... + ccLockDoors = 1, // Запереть все двери + ccUnLockDoors = 2, // Отпереть все двери + ccUnLockDoorDrv = 3, // Отпереть дверь водителя + ccLockTrunk = 4, // Запереть багажник + ccUnLockTrunk = 5, // Отпереть багажник + ccLockHood = 6, // Запереть капот + ccUnLockHood = 7, // Отпереть капот + ccCloseWindows = 8, // Закрыть окна + ccOpenWindows = 9, // Открыть окна + ccService = 10, // включение режима Автосервис + ccDisarm = 11, // выключение режима Охраны + //reserved = 12, + ccArm = 13, // включение режима Охраны + //reserved = 14, + //reserved = 15, + ccAlarmOff = 16, // выключить Тревогу + ccAlarmOn = 17, // включить Тревогу + ccPanicOff = 18, // выключение режима Паника + ccPanicOn = 19, // включение режима Паника + ccImmobilizerOff = 20, // выключить Иммобилайзер + ccImmobilizerOn = 21, // включить Иммобилайзер + ccIgnSupportOff = 22, // выключение поддержки зажигания + ccIgnSupportOn = 23, // включение поддержки зажигания + ccBlockageOff = 24, // выключить блокировку + ccBlockageOn = 25, // включить блокировку + ccEngineStart = 26, // запуск двигателя (по ошибке, стало событием) + ccEngineStop = 27, // глушение двигателя (по ошибке, стало событием) + ccTestMode = 28, // включение Тест-режима + ccFoldMirrors = 29, // сложить зеркала + ccUnFoldMirrors = 30, // разложить зеркала + ccCloseSunroof = 31, // закрыть люк + ccHeatedSeatsOn = 32, // включить подогрев сидений + ccHeatedSeatsOff = 33, // выключить подогрев сидений + ccPreHeaterOff = 34, // выключить предпусковой подогреватель + ccPreHeaterOn = 35, // включить предпусковой подогреватель + ccAutoStartOff = 36, // выключение запуска + ccAutoStartOn = 37, // включение запуска + ccAutoStartDone = 38, // успешный запуск + ccKillEngine = 39, // заглушить двигатель! + ccImmoBypass = 40, // обходчик иммобилайзера: бит 0 - включить; бит 1 - режим обучения + ccUpdateVin = 41, // обновить VIN-код + ccSendObdReq = 42, // запрос OBD-диагностики + ccValetMenuCmd = 43, // команда из меню антенны + ccHeatedWindowsOn = 44, // включить подогрев окон + ccHeatedWindowsOff = 45, // выключить подогрев окон +}; + +// Параметры команд для CAN прошивки, битовая маска (всего 24 бита) +enum TCanFwCommandParam : uint32_t { + mccReserved = (1 << 0), // резерв + mccSilent = (1 << 1), // беззвучное исполнение команды + mccPriority = (1 << 2), // приоритетное открытие двери водителя (ccDisarm) + mccDriveBuiltinSystem = (1 << 3), // разрешено управлять штатной охранной системой (ccLockTrunk/ccUnLockTrunk) +}; + +// данные, которые CAN-прошивка может передать в ядро +enum TCanFwData : uint8_t { + + CanData_RPM = 0, // обороты, об/мин + CanData_Speed = 1, // скорость, км/ч + CanData_Odometer = 2, // пробег, 1 ед = 100 метров + + CanData_Accelerator = 3, // положение педали газа, проценты + CanData_BrakeForce = 4, // положение педали тормоза, проценты + CanData_WheelAngle = 5, // положение руля + + CanData_FuelLevel = 6, // уровень топлива, проценты + CanData_FuelConsumption = 7, // мгновенный расход, миллилитры + + CanData_CoolantTemp = 8, // температура двигателя, со смещением 40 градусов + + CanData_VIN = 9, // VIN-код + + CanData_FuelLevelRaw = 10, // уровень топлива, без калибровки 0..255 + + CanData_COUNT, // количество возможных полей с данными + CanData_Invalid = 0x80, +}; + +// описание CAN-прошивки +extern const TCanFwInfo gCanFwInfo; + +// структура с функциями CAN, которые вызываются из ядра +struct TCanFunctions +{ + TCanFwInfo const * pCanFwInfo; + uint8_t const * pSettingsTable; + char const * const * pSettingsNames; + + void (*Init)(TCanFwMem * vars); + + void (*Periodic)(TCanFwMem * vars); + + void (*SettingChanged)(TCanFwMem * vars, uint16_t id); + void (*Reserved6)(); + + void (*InputChanged)(TCanFwMem * vars, uint32_t aInput, bool aSwitchedOn); + void (*OutputChanged)(TCanFwMem * vars, uint32_t aOutput, bool aSwitchedOn); + void (*GuardEvent)(TCanFwMem * vars, TGuardEvents aEvent); + + void (*Can1Received)(TCanFwMem * vars, TCanPkt *apPkt); + void (*Can2Received)(TCanFwMem * vars, TCanPkt *apPkt); + + void (*SequenceStart)(TCanFwMem * vars, uint32_t aOutputNum); + void (*SequenceStop)(TCanFwMem * vars, uint32_t aOutputNum); + + void (*Command)(TCanFwMem * vars, TCanFwCommands aCmd, uint32_t aCmdParam); + + void (*Lin1Received)(TCanFwMem* vars, TLinFrame* apFrame); + void (*Lin2Received)(TCanFwMem* vars, TLinFrame* apFrame); + void (*Lin1Transmitted)(TCanFwMem* vars, uint8_t aFrameId); + void (*Lin2Transmitted)(TCanFwMem* vars, uint8_t aFrameId); +#if defined MOBICAR_1_2 + void (*Reserved19)(); + void (*Reserved20)(); +#elif defined MOBICAR_3 || defined MAGICAR_X + void (*Lin3Received)(TCanFwMem * vars, TLinFrame *apFrame); + void (*Lin3Transmitted)(TCanFwMem * vars, uint8_t aFrameId); +#endif + + void (*Reserved21)(); + void (*Reserved22)(); + void (*Reserved23)(); + void (*Reserved24)(); + void (*Reserved25)(); + void (*Reserved26)(); + void (*Reserved27)(); + void (*Reserved28)(); + void (*Reserved29)(); + void (*Reserved30)(); + void (*Reserved31)(); +}; +static_assert (sizeof(TCanFunctions) == 4*32, "В таблице должно быть 32 поля"); + +// структура с функциями ядра, которые вызываются из CAN-прошивки +struct TCoreFunctions +{ + const TCoreInfo* pCoreInfo; + + uint32_t (*GetTickMs) (); + + uint32_t (*CanInit) (TCanChannel aCh, const TCanInit* apInit); + uint32_t (*CanSend) (TCanChannel aCh, TCanPkt* apPkt, uint32_t timeout); + + uint64_t (*GetInputs) (); + uint64_t (*GetOutputs) (); +#if defined MOBICAR_3 && 1 // Только для отладки (работает только с отладочной или спец. прошивками) + typedef struct { + uint8_t BlinkOff; // [50ms] + uint8_t BlinkOn; // [50ms] + uint8_t BeepTime; // [50ms] + uint8_t BeepTone; + } TDebugIndicate; + void (*DebugIndicate)(TDebugIndicate const & aIndicate, const uint8_t nBlink); +#else + void (*Reserved6)(); +#endif + + uint32_t (*Command) (TCoreCommands aCmd, uint32_t aParam); + uint32_t (*RunSequence) (uint32_t aOutput, uint32_t aSequenceNum); + + uint32_t (*SetPeriod) (uint32_t aPeriod); + + uint32_t (*SetOutput) (uint32_t aOutput, bool On); + + uint32_t (*InputState) (uint32_t aInput, bool On); + uint32_t (*DataValue) (uint32_t aDataIdx, int32_t aValue); + + uint32_t (*CanGetRxTimeout) (TCanChannel aCh); + + uint32_t (*LinInit) (TLinChannel aCh, const TLinInit* apInit); + uint32_t (*LinSend) (TLinChannel aCh, const TLinFrame* apFrame); + uint32_t (*LinSleep) (TLinChannel aCh, bool aSleep); + void (*Reserved17)(); + + uint32_t (*DataValueArr) (uint32_t aDataIdx, const void * data); + bool (*CheckVinValid) (); + bool (*SaveSetting) (uint16_t id, const void * apData, uint16_t aDataSize); + const void *(*GetSetting) (uint16_t id); + + bool (*SaveImmoLearn) (const void *data, uint32_t dataSize); + + void (*Reserved23)(); + void (*Reserved24)(); + void (*Reserved25)(); + void (*Reserved26)(); + void (*Reserved27)(); + void (*Reserved28)(); + void (*Reserved29)(); + void (*Reserved30)(); + + void (*DebugConsole)(const char *, ...); +}; +static_assert (sizeof(TCoreFunctions) == 4*32, "В таблице должно быть 32 поля"); + +// таблица с доступными функциями ядра + #define CoreFunc ((TCoreFunctions*) ((uint32_t) &FW_AREAS->Core + 512) ) // 16K + 512 + +#if defined CAN_FIRMWARE +// объявление функций CAN-прошивки + +void Init (TCanFwMem * vars); +void SettingChanged (TCanFwMem * vars, uint16_t id); + +void Can1Received (TCanFwMem * vars, TCanPkt *apPkt); +void Can2Received (TCanFwMem * vars, TCanPkt *apPkt); + +void InputChanged (TCanFwMem * vars, uint32_t aInputNum, bool aSwitchedOn); +void OutputChanged (TCanFwMem * vars, uint32_t aOutputNum, bool aSwitchedOn); +void GuardEvent (TCanFwMem * vars, TGuardEvents aEvent); + +void SequenceStart (TCanFwMem * vars, uint32_t aEvent); +void SequenceStop (TCanFwMem * vars, uint32_t aEvent); + +void Command (TCanFwMem * vars, TCanFwCommands aCmd, uint32_t aCmdParam); + +void PeriodicProcess (TCanFwMem * vars); + +void Lin1Received (TCanFwMem * vars, TLinFrame *apFrame); +void Lin2Received (TCanFwMem * vars, TLinFrame *apFrame); +void Lin3Received (TCanFwMem * vars, TLinFrame *apFrame); + +void Lin1Transmitted (TCanFwMem * vars, uint8_t aFrameId); +void Lin2Transmitted (TCanFwMem * vars, uint8_t aFrameId); +void Lin3Transmitted (TCanFwMem * vars, uint8_t aFrameId); + +#else // core + +// таблица с доступными функциями CAN-прошивки, лежит в её начале + #define CanFwFunc ((TCanFunctions*) &FW_AREAS->CanFw) + +#endif + +#endif /* CANFWINTERFACE_H_ */ diff --git a/libs/CanSources.cpp b/libs/CanSources.cpp new file mode 100644 index 0000000..10c6186 --- /dev/null +++ b/libs/CanSources.cpp @@ -0,0 +1,56 @@ +/* + * CanSources.cpp + * + * Created on: 01 дек. 2015 г. + * Author: esaulenko + */ + + + +#include "source/SourcePath.h" + +#ifdef SRC_HEADER +#include SRC_HEADER +#endif + +#ifdef SRC_FILE1 +#include SRC_FILE1 +#endif + +#ifdef SRC_FILE2 +#include SRC_FILE2 +#endif + +#ifdef SRC_FILE3 +#include SRC_FILE3 +#endif + +#ifdef SRC_FILE4 +#include SRC_FILE4 +#endif + +#ifdef SRC_FILE5 +#include SRC_FILE5 +#endif + +#ifdef SRC_FILE6 +#include SRC_FILE6 +#endif + +#ifdef SRC_FILE7 +#include SRC_FILE7 +#endif + +#ifdef SRC_FILE8 +#include SRC_FILE8 +#endif + +#ifdef SRC_FILE9 +#include SRC_FILE9 +#endif + +#ifdef SRC_FILE10 +#include SRC_FILE10 +#endif + + diff --git a/libs/CommonTypes.h b/libs/CommonTypes.h new file mode 100644 index 0000000..4a855f6 --- /dev/null +++ b/libs/CommonTypes.h @@ -0,0 +1,335 @@ +/* + * CommonTypes.h + * + * Created on: 16 апр. 2015 г. + * Author: esaulenko + */ + +#ifndef COMMON_COMMONTYPES_H_ +#define COMMON_COMMONTYPES_H_ + +#include + +#define member_size(type, member) sizeof(((type*)nullptr)->member) + +//typedef uint8_t byte; +//typedef uint16_t word; +typedef unsigned int uint; +typedef unsigned long ulong; + +//#define bbRAM(Var,Bit) ((uint*)(((uint)&Var + 0x22000000/32)*32))[Bit] +#define bbRAM(Var,Bit) ((volatile uint*)(((uint)&Var + SRAM_BB_BASE/32)*32))[Bit] +// !!! Начиная с компилятора версии 7, что-то в оптимизаторе изменилось.. и теперь, без volatile +// программа компилируется неверно. Поэтому добавляем признак volatile !!! + +#define KByte *1024 + +union TSysStateRecord +{ + uint16_t Record; + struct { + uint8_t Value; // Значение состояния Системы + uint8_t Check; // Проверка данных + } __attribute__((packed)); +} __attribute__((packed)); + +typedef TSysStateRecord TSysState[2 KByte / sizeof(TSysStateRecord)]; + +struct TFwRegions +{ +#if defined MOBICAR_1_2 +// страницы по 2 кбайта + const uint8_t Boot[16 KByte]; + const uint8_t Core[96 KByte]; + const uint8_t CanFw[16 KByte]; + const uint8_t Upload[96 KByte]; + const uint8_t Settings1[4 KByte]; + const uint8_t Settings2[4 KByte]; + const uint8_t Reserved[20 KByte]; + const uint8_t ImmoLearn[2 KByte]; + const TSysState SysState; +#elif defined MOBICAR_3 + const uint8_t Boot[16 KByte]; // sector 0 + const uint8_t Settings1[16 KByte]; // sector 1 + const uint8_t Settings2[16 KByte]; // sector 2 + const uint8_t CanFw[16 KByte]; // sector 3 + struct { + const uint8_t UploadAux[64 KByte - sizeof(TSysState)]; // sector 4 + const TSysState SysState; + } __attribute__((packed)); + union { + const uint8_t Upload[128 KByte]; // sector 5 + const uint8_t ImmoLearn[2 KByte]; + } __attribute__((packed)); + const uint8_t Core[2 * 128 KByte]; // sector 6, 7 +#endif +}; +#define FW_AREAS ((TFwRegions const *)0x08000000) + +// специальное значение для контрольной суммы - используется только в отладочной прошивке +#define CHKSUM_DEBUG 0xDebac0ab + +// битовая настройка, используется в модуле настроек. Для простоты реализации занимает в ОЗУ 1 байт. +typedef uint8_t bit_t; + +// ********** +// * Версия * +// ********** +union TVersion +{ + uint32_t Value; + struct { + uint8_t Day; + uint8_t Month; + uint8_t Year; + uint8_t Version; + } __attribute__((packed)); +} __attribute__((packed)); + +struct TBootInfo { + TVersion Version; // Версия загрузчика + uint16_t Build; // Номер билда загрузчика + uint8_t HwVer; // Версия железа + uint8_t Model; // Модель устройства. Mobicar1 = 0 (!), Mobicar2 = 2 + uint32_t SerialNumber; // Серийный номер устройства + uint32_t reserved2; + + uint8_t FirmwareKey[32]; // Ключ дешифрования прошивки + uint8_t ServerRegKey[12]; // ключ регистрации на сервере + uint8_t ServerExchKey[16]; // ключ установки соединения с сервером + uint32_t BluetoothPairingCode; // статический код для подшивания BLE устройств + + uint32_t reserved[120]; +} __attribute__((packed, aligned(4))); +#define TBootInfoSize __builtin_offsetof (TBootInfo, FirmwareKey) +static_assert (TBootInfoSize == 16, "TBootInfo changed!"); + +struct TCoreInfo { + TVersion Version; // Версия ПО + uint16_t Build; // Номер билда ядра + uint16_t reserved1; + uint32_t const * pCRC32; // Адрес, где расположена CRC32 в прошивке Ядра + uint32_t reserved2; + char TextInfo[64]; // Текстовая информация о прошивке Ядра +} __attribute__((packed, aligned(4))); +static_assert (sizeof(TCoreInfo) == 80, "TCoreInfo changed!"); + +// Структура массива информации о CAN-прошивке +struct TCanFwInfo { + TVersion Version; // Версия ПО + uint32_t Build; // Хеш коммита в репозитории git + uint32_t const * pCRC32; // Адрес, где расположена CRC32 + uint32_t reserved2; + uint8_t TextInfo[64]; // Текстовая информация +} __attribute__((packed, aligned(4))); +static_assert (sizeof(TCanFwInfo) == 80, "TCanFwInfo changed!"); + +// ******************** +// * НАСТРОЙКА ВХОДОВ * +// ******************** +struct TInputPinSettings { + uint16_t T1:14; // период активного импульса + uint16_t P1:2; // Подтяжка: [xy]: непрограммируемая(x=0)/программируемая(x=1)/pulldown(y=0)/pullup(y=1). + uint16_t T2:14; // период пассивного импульса + uint16_t P2:2; // Подтяжка: [xy]: непрограммируемая(x=0)/программируемая(x=1)/pulldown(y=0)/pullup(y=1). +// Таблица истинности: +// T1 P1 T2 P2 Debounce +// 0 p 0 x tick статика, без антидребезга +// >0 p 0 x T1 статика с периодом антидребезга равного T1 +// 0 p >0 p tick динамика, P1 включается на TICK, затем P2 включается на T2, без антидребезга. +// >0 p >0 p T1 динамика, P1 включается на T1*2, затем P2 включается на T2, антидребезг T1. +} __attribute__((packed)); + +struct TInputSettings { + uint8_t Input:7; // номер физического входа + uint8_t Invert:1; // Инвертировать состояние + + bool operator== (const TInputSettings &other) + { return *((uint8_t*)this) == *((uint8_t*)(&other)); } + bool operator!= (const TInputSettings &other) + { return ! (*this == other); } +} __attribute__((packed)); + +enum { + SequenceLength = 16, + maxSequences = 32, // кол-во импульсных последовательностей одновременно запущенных +}; + +// последовательности управления выходами +union TSequence { + uint8_t Byte[SequenceLength]; + union { + uint8_t Value; + struct { + uint8_t Mantissa:5; + uint8_t Power:3; + }; + } Step; +} __attribute__((packed)); + +typedef uint8_t TKeyAES[16]; // ключ шифрования радио + +typedef uint8_t TVehicleID[17]; // VIN-код + +//typedef uint8_t TImmoKey[124]; // ключ обходчика иммобилайзера +typedef uint8_t TImmoKey[32]; // ключ обходчика иммобилайзера + + +// настройка таймера запуска +struct TStartTimerSetting { + uint16_t Time; // количество минут с начала суток. У выключенного таймера биты инвертированы + uint8_t DayMask; // Биты дней недели, когда разрешён запуск - 0..6. Для "старого" механизма устанавливается 0xFF +} __attribute__((packed)); + +// CAN data forward declarations +struct TCanInit; +struct TCanPkt; + +enum TCanChannel { + CANch1 = 0, + CANch2 = 1, +}; + +enum TLinChannel { + LINch1 = 0, + LINch2 = 1, +#if defined MOBICAR_3 + LINch3 = 2, +#endif +}; + +enum TGuardEvents { + geSetSysMode = 0, // события о смене режима Системы + geRESET = 0, // событие сброс по Питанию + geTEST = 1, // включился режим Теста + geSERVICE = 2, // включился режим Автосервис + geDISARM = 3, // включился режим Вне Охраны + geHIJACK = 4, // включился режим Антизахват + geARM = 5, // включился режим Охрана + geGM6 = 6, // резерв + geGM7 = 7, // резерв + aseSetMode = 8, // события о смене режима Автозапуска + aseIDLE = 8, // Дежурный режим + aseREADY = 9, // Включение поддержки зажигания + asePRESTART_WaitForIgnOn = 10, // Подготовка к запуску двигателя: Ожидание включения Зажигания + asePRESTART_WaitForIgnOff = 11, // Подготовка к запуску двигателя: Ожидание выключения Зажигания + aseCRANK = 12, // Запуск двигателя (стартер) + asePRESUPPORT = 13, // + aseSUPPORT = 14, // Поддержка зажигания после запуска + asePITSTOP = 15, // Режим PITSTOP + aseSTOP = 16, // Режим STOP + aseISOFF = 17, // Режим ISOFF + aseDoorWag = 18, // Махание дверью + aseStopDoorWag = 19, // Остановка процесса махания дверью + aseSetIDLE = 20, // Переход в дежурный режим + aseSetREADY = 21, // Переход в режим поддержки зажигания + aseSetPITSTOP = 22, // Переход в режим PITSTOP + aseSetPRESTART = 23, // Переход в режим подготовки к запуску двигателя + aseSetSUPPORT = 24, // Переход в режим поддержки зажигания + aseSetSTOP = 25, // Остановка двигателя + aseSetISOFF = 26, // Выключение поддержки зажигания + aseLauncher = 27, // Мотор запущен внешним запуском + asePreHeater = 28, // Предпусковой подогреватель включен + aseASM21 = 29, // резерв + aseReloadTimer = 30, // продление/перезагрузка времени режима + aseCommandError = 31, // ошибка выполнения команды или не возможность выполнить команду +// Общие события + geLocked = 32, // ЦЗ закрыт + geUnLocked = 33, // ЦЗ открыт + geBlockageOff = 34, // Блокировка выключена + geBlockageOn = 35, // Блокировка включена + geReservationOff = 36, // Резервирование выключено + geReservationOn = 37, // Резервирование включено + geEngineStopped = 38, // Двигатель остановился + geEngineRuns = 39, // Двигатель завелся + geTurboTimerEnd = 40, // Турботаймер завершился + geTurboTimerStart = 41, // Турботаймер запустился + gePanicOff = 42, // выключился режим Паника + gePanicOn = 43, // включился режим Паника + geArmDefeatZone = 44, // оповещение об открытых зонах во время постановки в Охрану + geAlarmOff = 45, // выключился режим Тревоги + geAlarmOn = 46, // включить тревогу снова + geDoorsAlarm = 47, // включилась Тревога по дверям (салону) + geTrunkAlarm = 48, // включилась Тревога по багажнику + geHoodAlarm = 49, // включилась Тревога по капоту + geIgnAlarm = 50, // включилась Тревога по зажиганию + geShockAlarm = 51, // включилась Тревога по датчику Удара + geResetAlarm = 52, // включилась Тревога по сбросу Питания + geDoorsDefeated = 53, // отключилась охранная зона по двери + geTrunkDefeated = 54, // отключилась охранная зона по багажнику + geHoodDefeated = 55, // отключилась охранная зона по капоту + geIgnDefeated = 56, // отключилась охранная зона по зажиганию + geShockDefeated = 57, // отключилась охранная зона по датчику Удара + geTrunkOpened = 58, // багажник открыт + geTrunkClosed = 59, // багажник закрыт + geShockNotify = 60, // предупреждение по датчику Удара + geShockArmOff = 61, // оперативное отключение зоны датчика Удара + geCarOwnerCall = 62, // вызов владельца автомобиля + geTiltAlarm = 63, // включилась Тревога по датчику Наклона + geTiltDefeated = 64, // отключилась охранная зона по датчику Наклона + geValetArm = 65, // событие поставить в Охрану в режиме Автосервис + geValetDisarm = 66, // событие снять с Охраны в режиме Автосервис + geAlarmEnd = 67, // событие прекращения тревоги + geTrunkUnLock = 68, // багажник отпирается или отперт + geTrunkLock = 69, // багажник запирается или заперт + geImHereOff = 70, // выключился механизм поиска Автомобиля на стоянке + geImHereOn = 71, // включился механизм поиска Автомобиля на стоянке + geMotionAlarm = 72, // включилась Тревога по датчику Перемещений + geMotionDefeated = 73, // отключилась охранная зона по датчику Перемещений + geArmed = 74, // Система встала под Охрану + geArmReturnOff = 75, // Перепостановка отключена + geArmReturnOn = 76, // Активирован режим перепостановки + geAux1Off = 77, // Доп.канал #1 выключен + geAux1On = 78, // Доп.канал #1 включен + geAux2Off = 79, // Доп.канал #2 выключен + geAux2On = 80, // Доп.канал #2 включен + geAux3Off = 81, // Доп.канал #3 выключен + geAux3On = 82, // Доп.канал #3 включен + geSensorAlarm = 83, // тревога по внешнему Сенсору + geSensorDefeated = 84, // отключилась охранная зона по входу от внешнего Сенсора + geHandsfreeDisabled = 85, // сообщение о временном запрете Автопостановки/Автоснятия + geHandsfreeEnabled = 86, // сообщение о разрешении Автопостановки/Автоснятия + geValetDisabledByImm = 87, // включение режима Автосервис заблокировано по причине активированного Иммобилайзера + geDisarmDisabledByTag = 88, // снятие с Охраны заблокировано по причине отсутствия Метки + geUnTrunkDisabledByTag = 89, // отпирание багажника заблокировано по причине отсутствия Метки + geImmoIndicationStart = 90, // индикация включенного иммобилайзера + geSensorNotify = 91, // предупреждение по внешнему Сенсору + geDrivingEnabled = 92, // поездка разрешена (иммобилайзер был отключен ПИН кодом) + geTripFinish = 93, // Поездка закончилась + geTripStart = 94, // Поездка началась + geTripPaused = 95, // Поездка приостановилась + +// Команды Брелока (176+) + bcSendState = 0xB0, // Выслать текущий режим Системы (она же ресинхронизация) + bcChangeSoundMode, // Изменение режима выдачи звуков + bcChangeShockMode, // Изменение режима работы датчика Удара + bcChangeAutomatics, // Изменения в режимах работы Автоматических запусков + bcChangeInternetOption, // Изменения в режиме работы INTERNET опции + bcProgMenuEnter, // Перевести брелок в меню программирования + bcProgMenuExit, // Выход из меню программирования Брелока + vmShowPinCode, // Показать на индикаторе текущее значение ПИН-кода + bcProgMenu2, // Переход к меню 2 + bcBleMenuEnter, // Переход к меню спаривания BLE + bcHandsfreeModeChange, // Изменение режима работы "Свободных рук" + + geDEBUG = 0xFE, + geNONE = 0xFF // нет события, т.е. его не нужно никуда отправлять +}; + +union TDiagnosticTroubleCode { + uint16_t B1B0; + uint8_t Byte[2]; + struct { + uint8_t B0; + uint8_t B1; + } __attribute__((packed)); + struct { + uint16_t X:4; + uint16_t N:2; + uint16_t K:2; + uint16_t Z:4; + uint16_t Y:4; + } __attribute__((packed)); +} __attribute__((packed)); + +#endif /* COMMON_COMMONTYPES_H_ */ diff --git a/libs/IO.h b/libs/IO.h new file mode 100644 index 0000000..5127696 --- /dev/null +++ b/libs/IO.h @@ -0,0 +1,329 @@ +/* + * IO.h + * + * Created on: 11 июня 2015 г. + * Author: esaulenko + */ + +#ifndef DRIVERS_IO_H_ +#define DRIVERS_IO_H_ + +#include +#include "CommonTypes.h" +#include "Settings.h" +#include "Utils.h" + +#if not defined CAN_FIRMWARE +#include "SysTimer.h" +#endif + + +typedef uint64_t TInpMask; // битовая маска логических входов +typedef uint64_t TOutMask; // битовая маска логических выходов + +// макросы для более простого обращения к битовым маскам +#define oBIT(x) BIT64(CIO::x) +#define iBIT(x) BIT64(CIO::x) + + +class CIO +{ + #define iPIN(x) (CSettings::x-CSettings::ipOFFSET) + #define oNAME(x) (CSettings::x-CSettings::oOFFSET) + #define iNAME(x) (CSettings::x-CSettings::iOFFSET) + +public: + +// Эта таблица источников для логических входов (функций) +#if defined MOBICAR_1_2 + + enum TInPins { + iRedBlack = iPIN(iRedBlack), // Pin_Door_I + iGreyBlack = iPIN(iGreyBlack), // Pin_Trunk_I + iBrownBlack = iPIN(iBrownBlack), // Pin_Hood_I + iGreen = iPIN(iGreen), // Pin_Ignition + iLBlueBlack = iPIN(iLBlueBlack), // Pin_Parking_I + iBlackWhite = iPIN(iBlackWhite), // Pin_Foot_I + iBlackPink = iPIN(iBlackPink), // Pin_RPM_I + iYellowBlue = iPIN(iYellowBlue), // Pin_OutRes2 + iYellowWhite = iPIN(iYellowWhite), // Pin_OutRes1 + + ipCOUNT = CSettings::ipCOUNT, // Общее кол-во физических источников + + iCAN = 0x7E, // берется из CAN шины + iNone = 0x7F // никуда не подключен + }; + + enum TOutPins { + oBrownGreen, // Pin_Ign_O + oBrownViolet, // Pin_Ign1_O + oBrownYellow, // Pin_Start_O + oBrownWhite, // Pin_Acc_O + oGreen, // Pin_LockRelay Relay3 + oYellow, // Pin_UnlockRelay Relay4 + oVioletYellow, // Pin_Light1Relay Relay1 + oVioletBrown, // Pin_Light2Relay Relay2 + oPink, // Pin_Relay5 Relay5 + oBlue, // Pin_Immo_O + oBrown, // Pin_SirenOut + oYellowBlue, // Pin_OutRes2_O + oYellowWhite, // Pin_OutRes1_O + oOrange, // Kline1 + oOrangeBlack, // KLine2 + opCOUNT, // Общее кол-во физических выходов + oCAN = 31, + }; + +#elif defined MOBICAR_3 || defined MAGICAR_X + + enum TInPins { + iRedBlack = iPIN(iRedBlack), + iGreyBlack = iPIN(iGreyBlack), + iBrownBlack = iPIN(iBrownBlack), + iGreen = iPIN(iGreen), + iLBlueBlack = iPIN(iLBlueBlack), + iBlackWhite = iPIN(iBlackWhite), + iBlackPink = iPIN(iBlackPink), + iYellowBlue = iPIN(iYellowBlue), + iYellowWhite = iPIN(iYellowWhite), + + ipCOUNT = CSettings::ipCOUNT, // Общее кол-во физических источников + + iCAN = 0x7E, // берется из CAN шины + iNone = 0x7F // никуда не подключен + }; + + enum TOutPins { + oGreenRelay, + oVioletRelay, + oYellowRelay, + oWhiteRelay, + oBrownGreen, + oBrownYellow, + oBrownViolet, + oBrownWhite, + oOrangeBreak, // разрыв Lin1 + oBlue, + oBrown, + oYellowBlue, // вход/выход +/- + oYellowWhite, // вход/выход +/- + oGreen, // вход/выход + oBlackWhite, // вход/выход + oPinkBreak, // разрыв Lin2 + oOrange, // Lin1 + oPink, // Lin2 + oPinkWhite, // Lin3 + + opCOUNT, // Общее кол-во физических выходов + oCAN = 31 // Выход на CAN-прошивку + }; + +#else + #error IO pins: unknown model! +#endif + + enum TInputs { + iDoorDrv = iNAME(iDoorDrv), + iDoorFP = iNAME(iDoorFP), + iDoorRL = iNAME(iDoorRL), + iDoorRR = iNAME(iDoorRR), + iTrunk = iNAME(iTrunk), + iHood = iNAME(iHood), + iIgn = iNAME(iIgn), + iHBrake = iNAME(iHBrake), + iLamp = iNAME(iLamp), + iPark = iNAME(iPark), + iBrake = iNAME(iBrake), + iLeftTurnLight = iNAME(iLeftTurnLight), + iRightTurnLight = iNAME(iRightTurnLight), + iArm = iNAME(iArm), + iSensorAlarm = iNAME(iSensorAlarm), + iSensorNotify = iNAME(iSensorNotify), + iEngine = iNAME(iEngine), + iLock = iNAME(iLock), + iPreHeater = iNAME(iPreHeater), + iLowFuelLevel = iNAME(iLowFuelLevel), + iACC = iNAME(iACC), + iKeyIn = iNAME(iKeyIn), + iSpark = iNAME(iSpark), + iDoorsLamp = iNAME(iDoorsLamp), + iTrunkLamp = iNAME(iTrunkLamp), + iTrunkWindow = iNAME(iTrunkWindow), + iStartStop = iNAME(iStartStop), + iNeutral = iNAME(iNeutral), + iLauncher = iNAME(iLauncher), + iDisarm = iNAME(iDisarm), + iUnTrunk = iNAME(iUnTrunk), + iUnLock = iNAME(iUnLock), + + iDevice1 = iNAME(iDevice1), + iDevice2 = iNAME(iDevice2), + iDevice3 = iNAME(iDevice3), + iDevice4 = iNAME(iDevice4), + iDevice5 = iNAME(iDevice5), + iDevice6 = iNAME(iDevice6), + iDevice7 = iNAME(iDevice7), + iDevice8 = iNAME(iDevice8), + + iCOUNT = CSettings::iCOUNT, + + iStateAtMt = 63 // особый вход: "трансмиссия автомат" + }; + +// Виртуальные выходы на исполнительные устройства или +// выход на устройство выполняющее определенную функцию + enum TOutputs { + // Неопределенные устройства + oDevice1 = oNAME(oDevice1), // 0 + oDevice2 = oNAME(oDevice2), // 1 + oDevice3 = oNAME(oDevice3), // 2 + oDevice4 = oNAME(oDevice4), // 3 + oDevice5 = oNAME(oDevice5), // 4 + oDevice6 = oNAME(oDevice6), // 5 + oDevice7 = oNAME(oDevice7), // 6 + oDevice8 = oNAME(oDevice8), // 7 + // Базовые устройства Охранной системы + oSiren = oNAME(oSiren), // 08 Сирена + oHorn = oNAME(oHorn), // 09 Клаксон + oLights = oNAME(oLights), // 10 Поворотники + oLamp = oNAME(oLamp), // 11 Головное освещение + oPassiveBlockage = oNAME(oPassiveBlockage), // 12 Пассивная блокировка (когда выключена, цепь разомкнута, блокировка включена) + oActiveBlockage = oNAME(oActiveBlockage), // 13 Активная блокировка (когда выключена, цепь замкнута, блокировка выключена) + oLockDoors = oNAME(oLockDoors), // 14 Запереть все двери + oUnlockDoors = oNAME(oUnlockDoors), // 15 Отпереть все двери + oUnlockDoorDrv = oNAME(oUnlockDoorDrv), // 16 Отпереть дверь водителя + oLockTrunk = oNAME(oLockTrunk), // 17 Запереть багажник + oUnlockTrunk = oNAME(oUnlockTrunk), // 18 Отпереть багажник + oLockHood = oNAME(oLockHood), // 19 Запереть Капот + oUnLockHood = oNAME(oUnLockHood), // 20 Отпереть капот + oCloseWindows = oNAME(oCloseWindows), // 21 Закрыть окна + oPreHeaterOn = oNAME(oPreHeaterOn), // 22 Включение предпускового подогревателя + oPreHeaterOff = oNAME(oPreHeaterOff), // 23 Выключение предпускового подогревателя + oImmOn = oNAME(oImmOn), // 24 Устройство включающее Иммобилайзер + oImmOff = oNAME(oImmOff), // 25 Устройство выключающее Иммобилайзер + oService = oNAME(oService), // 26 Устройство переводящее автомобиль в Сервисный режим + oDisarm = oNAME(oDisarm), // 27 Устройство осуществляющее снятие с Охраны (можно использовать как выход статической блокировки) + oArm = oNAME(oArm), // 28 Устройство осуществляющее постановку под Охрану (можно использовать как выход статической блокировки) + oAlarm = oNAME(oAlarm), // 29 Устройство осуществляющее включение тревоги (можно использовать как выход статической блокировки) + oAutoStart = oNAME(oAutoStart), // 30 Состояние Автозапуска + // Базовые устройства АвтоЗапуска (подменяют или имитируют присутствие водителя в автомобиле) + oDoorWag = oNAME(oDoorWag), // 31 Устройство махающее дверью + oIgn = oNAME(oIgn), // 32 Включение зажигания + oBrake = oNAME(oBrake), // 33 Педаль тормоза + oKeyIn = oNAME(oKeyIn), // 34 Ключ в замке + oAcc = oNAME(oAcc), // 35 Аксессуары +// oBrakeControl = oNAME(oBrakeControl), // 36 Отключение контроля педали тормоза + oAuxBrake = oNAME(oAuxBrake), // 37 Дополнительная линия педали тормоза + oAuxIgn = oNAME(oAuxIgn), // 38 Дополнительная линия зажигания + oSSButton = oNAME(oSSButton), // 39 Кнопка Старт/Стоп + oImmBypass = oNAME(oImmBypass), // 40 Обходчик встроенного иммобилайзера + oCrank = oNAME(oCrank), // 41 Стартер + oCrankDisable = oNAME(oCrankDisable), // 42 Блокировка Стартера + // Дополнительные + oLockIgn = oNAME(oLockIgn), // 43 Блокировка зажигания (когда включена, зажигание заблокировано) + oUnLockIgn = oNAME(oUnLockIgn), // 44 Разблокировка зажигания (когда включена, зажигание разблокировано) + oKLine1Relay = oNAME(oKLine1Relay), // 45 Устройство коммутирующее KLine интерфейс + oAux1 = oNAME(oAux1), // 46 Доп.канал #1 + oAux2 = oNAME(oAux2), // 47 Доп.канал #2 + oAux3 = oNAME(oAux3), // 48 Доп.канал #3 + oEmergencyBraking=oNAME(oEmergencyBraking), // 49 Выход сигнала экстренного торможения + oIllumination = oNAME(oIllumination), // 50 Выход сигнала вежливой подсветки + oFoldMirrors = oNAME(oFoldMirrors), // 51 Сложить зеркала + oUnfoldMirrors = oNAME(oUnfoldMirrors), // 52 Разложить зеркала + oCloseSunroof = oNAME(oCloseSunroof), // 53 Закрыть люк + oMoveSunroof = oNAME(oMoveSunroof), // 54 Сдвинуть люк + oHeatedSeats = oNAME(oHeatedSeats), // 55 Обогрев сидений + oTriggerDoors = oNAME(oTriggerDoors), // 56 Триггерная кнопка ЦЗ + oIgnSupport = oNAME(oIgnSupport), // 57 Состояние поддержки зажигания + oArmWithoutTag = oNAME(oArmWithoutTag), // 58 Состояние "Охрана без метки" + oHeatedWindows = oNAME(oHeatedWindows), // 59 Обогрев окон + oKLine2Relay = oNAME(oKLine2Relay), // 60 m34x46: Коммутация Lin2 + oDVR = oNAME(oDVR), // 61 m34x46: Выход на видеорегистратор + // Общее кол-во виртуальных устройств + oCOUNT = CSettings::oCOUNT, + }; + +// режимы входов + enum TInputActiveState { + ActiveGND = 1 // Активное состояние, когда на входе GND + }; + +// режимы подтяжек входов + enum TInputPullupMode { + PullNone = 0, + PullDown = 2, + PullUp = 3, + }; + + #undef iPIN + #undef oNAME + #undef iNAME + +#ifndef CAN_FIRMWARE + + void Init(void); + void UpdateSettings(const uint idSettings); + +// проверка, что вход (физический) используется + static bool IsInputMapped(TInPins aPhInput); + +// чтение и обработка мгновенных состояний входов для получения устойчивых физических состояний + uint32_t ReadInputPins(void); +// Конвертирование переданных физический состояний (REMAP) в соответствующие логические состояния + TInpMask RemapInputs(uint32_t iPins); + +// установка физических выходов + void SetOutPhys(const TOutPins pin, const bool state); + +// Установка логических выходов. +// Возвращает: + enum TSetOutputResult : uint { + soNone = 0, // нет такого выхода или он никуда не назначен + soExist = 1, // Выход назначен, но состояние не изменилось + soChanged = 2 // выход назначен и состояние было изменено + }; + TSetOutputResult SetOutput(const TOutputs aOutput, const bool state); +// Запрос текущего состояния логического выхода + inline bool GetOutput(const TOutputs Output) const {return bbRAM(oStates,Output);}; + +// Вернуть состояние логических выходов (функций выходов) + inline TOutMask GetOutputs(void) const {return oStates;} +// Вернуть состояние логических входов (функций входов) + inline TInpMask GetInputs(void) const {return iStates;} +// Вернуть состояние физических выходов + inline uint32_t GetOutPhys(void) const {return opStates;} + inline bool GetOutPhys(const TOutPins pin) const + { return GetOutPhys() & BIT(pin); } + +// петля "тип коробки" + static bool StateAtMt(void); + +private: + TOutMask oStates; // сохраненные состояния логических выходов (всех функций выходов) + TInpMask iStates; // сохраненные состояния логических входов (всех функций входов) + uint32_t ipStates, ipTemp; // физические состояния входов, очищенные от дребезга... + uint32_t opStates; // физические состояния выходов + + struct TInputPin { + TimerMs Timer; + uint16_t TimeOut; + uint8_t Stage; + }; + TInputPin iPin[ipCOUNT]; + +// получение мгновенных состояний со входов + static uint32_t GetInputPins(void); + +// управляет состояниями подтяжек на входах + static void SetPullInput(TInPins Input, TInputPullupMode Mode); + + inline void ClrOutputState(TOutputs Output) {bbRAM(oStates,Output) = 0;}; + inline void SetOutputState(TOutputs Output) {bbRAM(oStates,Output) = 1;}; + +#endif // ! CAN_FIRMWARE +}; + +// глобальный объект портов ввода-вывода +extern CIO gIO; + +#endif /* DRIVERS_IO_H_ */ diff --git a/libs/LinBus.h b/libs/LinBus.h new file mode 100644 index 0000000..08369ef --- /dev/null +++ b/libs/LinBus.h @@ -0,0 +1,212 @@ +/* + * LinBus.h + * + * Created on: 17 дек. 2015 г. + * Author: esaulenko + */ + +#ifndef DRIVERS_LINBUS_H_ +#define DRIVERS_LINBUS_H_ + +#ifndef CAN_FIRMWARE + +#include "KLineDrv.h" +#include "ImoDrv.h" +#include "Buffer.h" +#include "SysTimer.h" +#include "scmRTOS/scmRTOS.h" + +extern CLin LinBus1; +extern CLin LinBus2; +extern CLin LinBus3; + +union TLinInit; + +#endif // CAN_FIRMWARE + +#include "LinFrame.h" + +class CLin +{ +public: + + enum TLinMode { + Mode_RawNoParity, // без стандарта, принимает-передаёт любые пакеты (без чётности) + Mode_Master, // LIN-мастер + Mode_Slave, // LIN-слейв + Mode_RawEvenParity, // без стандарта, байты с проверкой на чётность + Mode_RawOddParity, // без стандарта, байты с проверкой на нечётность + Mode_Raw9bit, // без стандарта, в байте 9 бит данных без чётности + Mode_RawIgnoreError, // без стандарта, принимаются байты без чётности, стоп-бита и т.д. + Mode_RawStop2bit, // без стандарта, 2 стоп-бита + Mode_ImoImi, // протокол Toyota (старый), 48.8 бит/сек, 16 бит данных + Mode_ImoRenault, // протокол Renault, 81,4 бит/с + Mode_ImoImi2, // протокол Toyota (новый), 195.3 бит/сек, 32 бита данных + Mode_FordDstTx, // протокол Ford DST80 (ШИМ, 1 бит = 1 мс / 0,5 мс) + Mode_FordUartRx, // протокол Ford (UART 15625 бит/с, 384 мкс между байтами) + Mode_Haval, // протокол с импульсами подтверждения (фильтрация/генерация) + Mode_FordDstInversion, // протокол Ford DST80 (ШИМ, 1 бит = 1 мс / 0,5 мс, ИНВЕРСНЫЙ сигнал) + }; + +#ifndef CAN_FIRMWARE + + CLin(const KLineHw & cfg) : _drv(cfg, this), _imoDrv(this, cfg) + {} + + uint32_t Init(const TLinInit & init); + + // Для режима Haval + void InitEXTI(void); + void DeinitEXTI(void); + void EdgeRcv(const bool newVal); + + void CheckTimeout(void); + + int32_t GetFrame(TLinFrame & aFrame); + + uint32_t SendFrame(const TLinFrame & aFrame); + + void Sleep(const bool sleepEnable); + +// вызывается из обработчиков прерываний: +// приём/передача UART + void IrqUart(void) + { _drv.IrqProcess(); } +// передача UART по таймеру + uint32_t IrqTimerSend(void) + { return _drv.IrqTimerSend(); } +// фронт в режиме IMO/IMI + void IrqImoEdge(const bool val) + { + Sleep(false); + if (_mode == Mode_Haval) + EdgeRcv(val); + else + _imoDrv.rx.EdgeRcv(val); + } +// таймер передачи в режиме IMO/IMI (только для LIN1) + void IrqImoSend(void) + { _imoDrv.tx.IrqSetNextBit(); } + +// управление выходом напрямую, как GPIO + void SetOutput(const bool setZero); + +private: + CKLineDrv _drv; + CImoDrv _imoDrv; + +// вызывается из прерывания по приёму + void DataRcvd(uint16_t data); + void BreakRcvd(void); + void ErrorRcvd(void); + +// вызывается из прерываний IMO/IMI + void DataImiRcvd(const uint8_t * data, uint32_t data_len); + +// вызывается из прерывания по передаче + bool IsTxData(void) + { return _tx_buf.Avail() > 0; } + uint16_t GetTxData(void) + { return _tx_buf.Get(); } + void TxComplete(void); + + friend CKLineDrv; + friend CImoDrv; + + TLinMode _mode; + + union { + bool _mode9bit = false; + bool _InverseSignal; // инверсия входного сигнала + }; + + // не-UART протоколы на таймере + bool isCustomMode(void) const + { + return _mode == Mode_ImoImi || + _mode == Mode_ImoImi2 || + _mode == Mode_ImoRenault || + _mode == Mode_FordDstTx || + _mode == Mode_FordDstInversion; + } + + enum { + State_NoInit, + State_BusOff, + State_Idle, + State_WaitSync, + State_WaitId, + State_WaitData, + State_SlaveTxData, + } _state = State_NoInit; + + TLinFrame _rx_frame; + TimerMs _rx_tmr; + uint32_t _rx_timeout; + + TimerMs _sleep_tmr; + uint32_t _sleep_timeout; + + uint8_t _bytecnt; // счетчик байт для Mode_Haval + uint8_t _bytes_noack; // кол-во байт без подтверждения для Mode_Haval + uint8_t _bytes_ack; // кол-во байт c подтверждением для Mode_Haval +// TimerUs _ack_tmr; // таймер для генерации импульов Mode_Haval + uint8_t _bit_length_us; + uint16_t _ack_pause_us; + + bool FrameToRxQueue(void); + CircularBuffer _rx_queue; + + CircularBuffer _tx_buf; // буфер на передачу + + TLinFrame _tx_fr_buf[16]; // кадры для передачи slave'ом + TLinFrame*_tx_fr_cur = _tx_fr_buf; // текущий передающийся кадр + bool StartSlaveTx(uint8_t id); // функция отправки этого кадра + + TLinFrame * getTxFrame(void) // забрать фрейм из буфера (для imo_drv) + { + for (auto & it: _tx_fr_buf) + if (it.data_len > 0) + return ⁢ + return nullptr; + } + +// возвращает номер канала + inline TLinChannel Instance(void) const + { +#ifdef MOBICAR_3 + if (this == &LinBus3) + return LINch3; +#endif + if (this == &LinBus2) + return LINch2; + return LINch1; + } + +#endif // not CAN_FIRMWARE + +}; + +union TLinInit +{ + struct TLin + { + uint16_t baudrate; + CLin::TLinMode mode; + uint32_t rxTimeout; + uint32_t sleepTimeout; + }Lin; + + struct THaval + { + uint16_t baudrate; + CLin::TLinMode mode; + uint16_t rxTimeout; + uint32_t sleepTimeout; + uint8_t bytes_noack; // кол-во байт без подтверждения + uint8_t bytes_ack; // кол-во байт c подтверждением + uint16_t ack_pause_us; // пауза в us перед ack в режиме генерации (0-режим фильтрации) + }Haval; +}; + +#endif /* DRIVERS_LINBUS_H_ */ diff --git a/libs/LinFrame.h b/libs/LinFrame.h new file mode 100644 index 0000000..4725b98 --- /dev/null +++ b/libs/LinFrame.h @@ -0,0 +1,81 @@ +/* + * LinFrame.h + * + * Created on: 26 дек. 2015 г. + * Author: esaulenko + */ + +#ifndef DRIVERS_LIN_LINFRAME_H_ +#define DRIVERS_LIN_LINFRAME_H_ + + +#include +#include "Utils.h" + + +class TLinFrame +{ +private: + enum { MaxDataLen = 16, }; + +public: + TLinFrame(): + data_len(-1) // изначально буфер пустой + {} + + uint8_t id; + int8_t data_len; // знак используется при приёме + uint16_t data[MaxDataLen + 1]; // data + chksum + + // посчитать контрольную сумму по стандарту 1.1 (без ID) или по стандарту 2.0 (c ID) + uint8_t CalcChksum (bool new_mode) + { + data_len = MIN (data_len, MaxDataLen); + uint32_t chksum = new_mode ? id : 0; + + for (int i = 0; i < data_len; i++) + { + chksum += data[i]; + if (chksum > 0xFF) + chksum -= 0xFF; + } + return ~ chksum; + } + + // добавить контрольную сумму в пакет + void AddChksum (bool new_mode) + { data[data_len] = CalcChksum (new_mode); } + + // проверить контрольную сумму пакета + bool IsChksumCorrect (bool new_mode) + { return data[data_len] == CalcChksum (new_mode); } + + // посчитать контрольные (старшие) биты в идентификаторе + void CalcIdChksum (uint8_t aId) + { + // byte = p7 p6 b5..b0 + // P6 = b0 ^ b1 ^ b2 ^ b4 + // P7 = ~ (b1 ^ b3 ^ b4 ^ b5) + + uint8_t P6 = (aId >> 0) ^ (aId >> 1) ^ (aId >> 2) ^ (aId >> 4); + uint8_t P7 = (aId >> 1) ^ (aId >> 3) ^ (aId >> 4) ^ (aId >> 5); + P6 = ( P6 & 0x01) << 6; + P7 = ((~P7) & 0x01) << 7; + + id = P7 | P6 | (aId & 0x3F); + } + + + // скопировать данные в кадр (до 8 байт) + template + inline void SetData (const char (&data_str)[N]) + { + data_len = MIN (N - 1, MaxDataLen); + for (int i = 0; i < data_len; i++) + data[i] = (uint8_t)data_str[i]; + } +}; + + + +#endif /* DRIVERS_LIN_LINFRAME_H_ */ diff --git a/libs/ModelName.h b/libs/ModelName.h new file mode 100644 index 0000000..7066afe --- /dev/null +++ b/libs/ModelName.h @@ -0,0 +1,9 @@ +#pragma once + + +#if defined MOBICAR_1_2 + #define M_NAME "M2_" +#elif defined MOBICAR_3 + #define M_NAME "M3_" +#endif + diff --git a/libs/Periodic.h b/libs/Periodic.h new file mode 100644 index 0000000..2112d32 --- /dev/null +++ b/libs/Periodic.h @@ -0,0 +1,166 @@ +/* + * Periodic.h + * + * Создан: 09 окт. 2015 г. + * Автор: esaulenko + * + * Изменен: 21 ноя. 2019 г. + * Автор: gavrilov + */ + +#ifndef PERIODIC_H_ +#define PERIODIC_H_ + +#include +#include +#include "SysTimer.h" +#include "Utils.h" + +template +class CPeriodic +{ +private: + typedef void (* TPeriodicTask) (TCanFwMem * apMem); + +public: +// добавить новую функцию для периодического вызова. Обычно выполняется один раз. + void AddTask(const uint iTask, TPeriodicTask TaskHandler = nullptr, const uint32_t msTime = 0) + { + if (iTask < nTasks) + { + Tasks[iTask].Handler = TaskHandler; + SetTimeout(iTask, msTime); + } + } + +// Установить время, через которое надо будет вызвать периодическую функцию + void SetTimeout(const uint iTask, uint32_t msTime = 0) + { + if (iTask < nTasks) + {// индекс не превышает размер массива +// Если вызов происходит из , то местный таймер уже был сброшен.. и, соответственно, нужно только обновить +// значение периода.. а пересчет минимального времени, также произойдет при выходе из .. +// При вызове же вне , ни местный таймер не сбрасывается, ни пересчет периода не происходит.. + if (!Mutex) + {// При вызове вне : + // 1. Нужно обязательно вызывать метод , т.к. следующий период может как удлиниться, так и укоротиться. + // 2. А для того, чтобы метод правильно выставил время следующего вызова , + // требуется пересчитать все текущие периоды с учетом набега времени. + // 3. А раз нам требуется пересчитать все текущие периоды, то значит мы должны пересбросить местный + // таймер отсчета времени. + // 4. Однако, т.к. отсюда нельзя вызывать обработчики, то тем периодам, что окончились здесь, + // приходится ставить минимальное значение =1, чтобы обеспечить как можно скорее вызов обработчика . + // + auto elapsed = Timer.Restart(); + if (elapsed) + for (auto & Task: Tasks) + // Пройдемся по всем задачам.. + if (Task.Timeout) + { + // task enabled + if (Task.Timeout > elapsed) + Task.Timeout -= elapsed; + else + // Отсюда мы не можем вызвать обработчик, поэтому просто ставим минимальное время.. + Task.Timeout = 1; + } + } + if (Tasks[iTask].Handler == nullptr) + // Если обработчик неопределен.. остановить задачу.. + msTime = 0; + // Установить время.. + Tasks[iTask].Timeout = msTime; + // Всегда сбрасывать признак выполненной задачи, т.к. только-что для нее был выставлен новый период.. + // ..следовательно, предыдущий период уже стал неактуальным.. + Tasks[iTask].Done = false; + // Пересчитать интервалы.. + if (!Mutex) + // ..здесь только для вызывов извне .. + SetNextCall(); + } + } + +// остановить задачу + void Stop(const uint iTask) + { + if (iTask < nTasks) + { + Tasks[iTask].Timeout = 0; + Tasks[iTask].Done = false; + } + } + +// проверить, что задача запущена + bool isActive(const uint iTask) const + { + if (iTask < nTasks) + if (Tasks[iTask].Handler != nullptr) + if (Tasks[iTask].Timeout) + return true; + return false; + } + +private: + struct { + TPeriodicTask Handler = nullptr; + uint32_t Timeout = 0; + bool Done = false; + } Tasks[nTasks]; + + TimerMs Timer; + volatile bool Mutex = false; + +// Обработчик, вызывается из PeriodicProcess() + void Process(TCanFwMem * apCanMemory) + { + auto elapsed = Timer.Restart(); + if (elapsed) + { + // Сначала нужно обновить периоды всех периодических функций.. + for (auto & Task: Tasks) + // Пройдемся по всем задачам.. + if (Task.Timeout) + { + // task enabled + if (Task.Timeout > elapsed) + Task.Timeout -= elapsed; + else + { + Task.Done = true; + Task.Timeout = 0; + } + } + // Затем запустить все сработавшие задачи.. + Mutex = true; // выставить признак того, что метод будет вызван из метода + for (auto & Task: Tasks) + // Пройдемся по всем задачам.. + if (Task.Done) + {// Если задача сработала.. + Task.Done = false; + if (Task.Handler != nullptr) + // task exist + Task.Handler(apCanMemory); // ..запустить ее + } + Mutex = false; + // Запустить перерасчет и установку минимального интревала времени для вызова следующей периодической функции + SetNextCall(); + } + } + friend void PeriodicProcess(TCanFwMem * vars); + +// Расчитать минимальное значение интервала времени для вызова следующей периодической функции + void SetNextCall(void) + { + uint32_t minTime = UINT32_MAX; + for (const auto & Task: Tasks) + if (Task.Timeout) + if (Task.Timeout < minTime) + minTime = Task.Timeout; + + if (minTime == UINT32_MAX) + minTime = 0; // Остановить вызов + CoreFunc->SetPeriod(minTime); + } +}; + +#endif /* PERIODIC_H_ */ diff --git a/libs/Settings.cpp b/libs/Settings.cpp new file mode 100644 index 0000000..3673007 --- /dev/null +++ b/libs/Settings.cpp @@ -0,0 +1,67 @@ +/* + * Settings.cpp + * + * Created on: 12 мая 2015 г. + * Author: esaulenko + */ + +#include "Settings.h" +#include "IO.h" +#include "Utils.h" +#include "CanFwInterface.h" + + +// строки с названиями настроек +#define SETTING(...) +#define SETTING_CAN(...) +#define SETTING_RSRV(...) +#define SETTING_NAME(name, string) \ + __attribute__ ((section(".SettingsVarName"))) \ + static const char name ## String[] = string; +#include SRC_SETTINGS + +#undef SETTING +#undef SETTING_RSRV +#undef SETTING_ALIAS +#undef SETTING_CAN +#undef SETTING_NAME + + +// таблица с настройками CAN-прошивки +__attribute__ ((section(".SettingsTable"))) +const CSettings::TCANSettingsTable CSettings::CanSettingsTable = { + #define SETTING(name, attr, type, def_val...) \ + name, kind_ ## type, attr, sizeof(THeader)+sizeof(type), def_val, + #define SETTING_CAN(name, attr, type, def_val, description) \ + name, kind_ ## type, attr, sizeof(THeader)+sizeof(type), def_val, + #define SETTING_RSRV(...) // не используется + #define SETTING_NAME(name, string) \ + name, 0x1F, NotFixed, sizeof(THeader)+sizeof(char*), name ## String, + + #include SRC_SETTINGS + +// 0xffff //LastVal + CSettings::LastVal +}; +#undef SETTING +#undef SETTING_RSRV +#undef SETTING_ALIAS +#undef SETTING_CAN +#undef SETTING_NAME + + +__attribute__ ((section(".SettingsCanName"))) +const char * const CSettings::CanSettingsName[] = { + #define SETTING(...) // names not used + #define SETTING_CAN(name, attr, type, def_val, description) description, + #define SETTING_RSRV(...) // не используется + #define SETTING_NAME(...) // не используется + + #include SRC_SETTINGS +}; +#undef SETTING +#undef SETTING_RSRV +#undef SETTING_ALIAS +#undef SETTING_CAN +#undef SETTING_NAME + diff --git a/libs/Settings.h b/libs/Settings.h new file mode 100644 index 0000000..c6e3f8f --- /dev/null +++ b/libs/Settings.h @@ -0,0 +1,267 @@ +/* + * Settings.h + * + * Created on: 12 мая 2015 г. + * Author: esaulenko + */ + +#ifndef COMMON_SETTINGS_H_ +#define COMMON_SETTINGS_H_ + +#include "CommonTypes.h" +#include "source/SourcePath.h" + +#ifdef SRC_TYPES +#include SRC_TYPES +#endif + +class CSettings +{ +public: +// глобальная структура с настройками + struct TSettings + { + #define SETTING(...) // не используется + #define SETTING_CAN(name, attrib, type, ...) type name; + #define SETTING_RSRV(...) // не используется + #define SETTING_NAME(...) // не используется + #include SRC_SETTINGS + } __attribute__((packed)); + #undef SETTING + #undef SETTING_RSRV + #undef SETTING_ALIAS + #undef SETTING_CAN + #undef SETTING_NAME + +// объявляем номера настроек. этот enum может расти только вниз! + enum TSettingsID : uint16_t + { + #define SETTING(name, ...) name, + #define SETTING_RSRV(name) name, + #define SETTING_ALIAS(name) name, + #include "SettingsTable.h" // настройки ядра + + CanSettingsStart = 0x600, // отсюда начинаются настройки CAN-прошивки (ПРИЧЕМ, самой 0x600 не может быть!!! т.к. это enum) + + #define SETTING(name, ...) // не используется + #define SETTING_RSRV(name) name, + #define SETTING_CAN(name,...) name, + #define SETTING_NAME(...) // не используется + #include SRC_SETTINGS // собственные настройки CAN-прошивки + + LastVal = 0x7FF // последний параметр + }; + #undef SETTING + #undef SETTING_RSRV + #undef SETTING_ALIAS + #undef SETTING_CAN + #undef SETTING_NAME + + +// значения по умолчанию + enum DefaultValues { + minTimeZone = -9, // значение <-9> из-за ограничения при ручной установке пояса с брелока + defTimeZone = 0, + maxTimeZone = 12, + defClockSyncMode = 2, + maxClockSyncMode = 2, + defTimeZoneSyncMode = 2, + maxTimeZoneSyncMode = 2, + + defLightsAutoStartMode = 2, + maxLightsAutoStartMode = 2, + defIlluminationMode = 0, + maxIlluminationMode = 3, + + defLockByDriveMode = 0, + maxLockByDriveMode = 3, + defUnlockByParkMode = 0, + maxUnlockByParkMode = 2, + + defArmReturnTimeIndex = 0, + minPlafondAlarmDelay = 1, + defPlafondAlarmDelay = 20,//60, + maxPlafondAlarmDelay = 120, + minDoorsLampDeciseconds = 0, + defDoorsLampDeciseconds = 30, + maxDoorsLampDeciseconds = 100, + minTrunkLampDeciseconds = 0, + defTrunkLampDeciseconds = 30, + maxTrunkLampDeciseconds = 100, + + minAlarmDoorsDeciseconds = 0, + defAlarmDoorsDeciseconds = 5, // 0.5сек по умолчанию + maxAlarmDoorsDeciseconds = 50, // 5сек максимум + minAlarmTrunkDeciseconds = 0, + defAlarmTrunkDeciseconds = 5, // 0.5сек по умолчанию + maxAlarmTrunkDeciseconds = 100, // 10сек максимум + minKillEngineDeciseconds = 10, // 1.0сек минимум + defKillEngineDeciseconds = 0x80, // по умолчанию, выключено + maxKillEngineDeciseconds = 127, // 12.7сек максимум + + defTurboTimerIndex = 0, + minReadyMinutes = 1, + defReadyMinutes = 2, + maxReadyMinutes = 8, + minSupportMinutes = 10, + defSupportMinutes = 20, + maxSupportMinutes = 60, + defPitStopTimeIndex = 1, + minPreHeaterMinutes = 1, + defPreHeaterMinutes = 10, + maxPreHeaterMinutes = 60, + defSetReadyMode = 0, + maxSetReadyMode = 2, + minManualAttempts = 1, + defManualAttempts = 1, + maxManualAttempts = 3, + defClrReadyMode = 0, + maxClrReadyMode = 1, + defPrestartSSB = 0, + maxPrestartSSB = 3, + defStopSSB = 0, + maxStopSSB = 3, + minCrankDelaySeconds = 1, + defCrankDelaySeconds = 3, + maxCrankDelaySeconds = 20, + minAutoStartBatteryLevel = 108, + defAutoStartBatteryLevel = 110|0x80, // выключено по-умолчанию + maxAutoStartBatteryLevel = 126, + minAutoStartTemperature = -30, + defAutoStartTemperature = 0-128, // выключена по-умолчанию + maxAutoStartTemperature = 60, + defDailyRunCountIndex = 0, + defAutomaticsPeriodIndex = 0, + defAutomaticsLimitIndex = 0, + minEngineStartPercent = 40/2, + defEngineStartPercent = 70/2, + maxEngineStartPercent = 100/2, + minEngineRunPercent = 30/2, + defEngineRunPercent = 60/2, + maxEngineRunPercent = 80/2, + minTurboTimerPercent = 150/2, + defTurboTimerPercent = 300/2, + maxTurboTimerPercent = 350/2, + + minExternalHeatersTemperature = -20, + defExternalHeatersTemperature = 0-128, // выключена по-умолчанию + maxExternalHeatersTemperature = 20, + + maxExternalTemperatureSensorType = 1, + + defEmergencyBraking = 2, + maxEmergencyBraking = 2, + + maxShockSensTable = 1, + + minWaitAnswerTimeout = 5, + defWaitAnswerTimeout = 20, + maxWaitAnswerTimeout = 60, + minCallEndTimeout = 5, + defCallEndTimeout = 10, + maxCallEndTimeout = 60, + minTripEndTimeout = 5, + defTripEndTimeout = 15, + maxTripEndTimeout = 60, + minLowBatteryVoltage = 110, + defLowBatteryVoltage = 118, + maxLowBatteryVoltage = 125, + }; + +private: + +// заголовок таблицы настроек + struct THeader + { + uint16_t ID :11; // идентификатор. Erase=0x000; Core=[0x001..0x5FF]; CanFw=[0x601..0x7FE]; LastVal=0x7FF + uint16_t Kind : 5; // тип данных, см. SettingKind + uint8_t Fixed : 1; + uint8_t Len : 7; // длина с учётом заголовка +// uint8_t Data[0]; + + bool operator == (const THeader & Header) const // fixed не проверяется! +// { return (ID == Header.ID) && (Kind == Header.Kind) && (Len == Header.Len); } +// { return (*(uint16_t*)this == *(uint16_t*)&Header) && (Len == Header.Len); } + { return (*(uint16_t*)this == *(uint16_t*)&Header); } // и длина не проверяется! + } __attribute__ ((packed)); // sizeof() = 3 + + enum { + minRecordSize = sizeof(THeader)+1, + maxRecordSize = sizeof(THeader)+124 // 127 = 3+124 - самый максимум, т.к. Len = 7 бит. + }; + + // список допустимых типов данных. + // важно! при добавлении новых необходимо расширять список! + enum SettingKind // 0..31 + { + kind_bit_t, + kind_uint8_t, + kind_uint16_t, + kind_uint32_t, + kind_int8_t, + kind_int16_t, + kind_int32_t, + kind_array_t, + kind_TInputPinSettings = kind_array_t, + kind_TInputSettings = kind_array_t, + kind_TSequence = kind_array_t, + kind_TCanOutMask = kind_array_t, + kind_uint64_t = kind_array_t, + kind_TKeyAES = kind_array_t, + kind_TVehicleID = kind_array_t, + kind_TStartTimerSetting = kind_array_t, + kind_TImmoKey = kind_array_t, + kind_TPhoneNumber = kind_array_t, + kind_TModemAPN = kind_array_t, + kind_TModemLogin = kind_array_t, + kind_TModemPassword = kind_array_t, + kind_TTagRSSI = kind_array_t, + + kind_SettingName = 0x1F // спецзначение - указатель на описание настройки в CAN-прошивке + }; + + enum SettingAttr + { + NotFixed = 0, + Fixed = 1, + }; + +// Подбор ближайшего множителя к указанным милисекундам: MUL = ((2^p - 1)*2^5) + m*2^p = 2^(p+5) - 2^5 + m*2^p = (m + 2^5)*2^p - 2^5 + static constexpr uint8_t qMS(int ms, int p = 0) + { return ms < ((127<>(p+1)) : p < 7 ? qMS(ms, p+1) : 0xFF; } + + +public: + + // таблица с настройками CAN-прошивки + struct TCANSettingsTable + { + #define SETTING(name, attr, type, ...) \ + THeader hdr_ ## name; type name; + #define SETTING_CAN(name, attr, type, ...) \ + THeader hdr_ ## name; type name; + + #define SETTING_RSRV(...) // не используется + #define SETTING_NAME(name,string) \ + THeader hdr_ ## name ## Str; const char * p ## name ## Str; + + #include SRC_SETTINGS + + #undef SETTING + #undef SETTING_RSRV + #undef SETTING_ALIAS + #undef SETTING_CAN + #undef SETTING_NAME + + uint16_t last_val; + } __attribute__ ((packed)); + +// таблица с настройками CAN-прошивки + static const TCANSettingsTable CanSettingsTable; + +// таблица с названиями полей CAN-прошивки + static const char * const CanSettingsName[]; + +}; + +#endif // COMMON_SETTINGS_H_ diff --git a/libs/SettingsTable.h b/libs/SettingsTable.h new file mode 100644 index 0000000..82df05d --- /dev/null +++ b/libs/SettingsTable.h @@ -0,0 +1,687 @@ + +// таблица с используемыми настройками + +// выше должно быть определение того, какие поля используются +//#define SETTING(name, attrib, type, def_val) + +// при добавлении новых типов данных необходимо расширить enum SettingKind + +// SETTING_RSRV позволяет сделать "дырки" в номерах настроек +// если не определена, значит, она не используется +#ifndef SETTING_RSRV +#define SETTING_RSRV(name) +#endif + +// SETTING_ALIAS позволяет задавать альтернативные имена для настроек +#ifndef SETTING_ALIAS +#define SETTING_ALIAS(alt_name) +#endif + +SETTING_RSRV(Erased = 0) // нулевая настройка используется при удалении какого-либо идентификатора. + +// настройки физических входов: 1..9 + 1 резерв +SETTING (iRedBlack, NotFixed, TInputPinSettings, {50, 3, 0}) +SETTING (iGreyBlack, NotFixed, TInputPinSettings, {50, 3, 0}) +SETTING (iBrownBlack, NotFixed, TInputPinSettings, {50, 3, 0}) +SETTING (iGreen, NotFixed, TInputPinSettings, {50, 0, 0}) +SETTING (iLBlueBlack, NotFixed, TInputPinSettings, {50, 1, 0}) +SETTING (iBlackWhite, NotFixed, TInputPinSettings, {50, 0, 0}) +SETTING (iBlackPink, NotFixed, TInputPinSettings, {50, 1, 0}) +SETTING (iYellowBlue, NotFixed, TInputPinSettings, {50, 1, 0}) +SETTING (iYellowWhite, NotFixed, TInputPinSettings, {50, 1, 0}) +#ifndef ipFIRST +#define ipFIRST iRedBlack +#endif +SETTING_ALIAS(ipLAST) + +SETTING_ALIAS(ipOFFSET = ipFIRST) +SETTING_ALIAS(ipCOUNT = (ipLAST-ipFIRST)) + +SETTING_RSRV(ReservedPins = 10) + +/* Значения по-умолчанию: +Connector input wires table for FW rev 198: + Red-black wire Doors input (active low) + Grey-black wire Trunk input (active low) + Brown-black wire Hood input (active low) + Green wire Ignition input (active high) + Blue-black wire Handbrake/parking input (active low) + Black-white wire Brake input (active high) + Black-pink wire Tachometer input +*/ +// настройки логических входов - 11..74 +// Состояние неопределенных устройств (объектов) +SETTING (iDevice1, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice2, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice3, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice4, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice5, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice6, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice7, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDevice8, NotFixed, TInputSettings, {CIO::iNone, 0}) +SETTING (iDoorDrv, NotFixed, TInputSettings, {CIO::iRedBlack, CIO::ActiveGND}) // дверь водитель +SETTING (iDoorFP, NotFixed, TInputSettings, {CIO::iRedBlack, CIO::ActiveGND}) // дверь переднего пассажира +SETTING (iDoorRL, NotFixed, TInputSettings, {CIO::iRedBlack, CIO::ActiveGND}) // дверь задняя левая +SETTING (iDoorRR, NotFixed, TInputSettings, {CIO::iRedBlack, CIO::ActiveGND}) // дверь задняя правая +SETTING (iTrunk, NotFixed, TInputSettings, {CIO::iGreyBlack, CIO::ActiveGND}) // багажник +SETTING (iHood, NotFixed, TInputSettings, {CIO::iBrownBlack, CIO::ActiveGND}) // капот +SETTING (iIgn, NotFixed, TInputSettings, {CIO::iGreen, 0}) // Зажигание +SETTING (iHBrake, NotFixed, TInputSettings, {CIO::iLBlueBlack, CIO::ActiveGND}) // ручник +SETTING (iLamp, NotFixed, TInputSettings, {CIO::iNone, 0}) // Головное освещение (фары) +SETTING (iPark, NotFixed, TInputSettings, {CIO::iLBlueBlack, CIO::ActiveGND}) // положение ПАРК +SETTING (iBrake, NotFixed, TInputSettings, {CIO::iBlackWhite, 0}) // педаль тормоза +SETTING (iLeftTurnLight, NotFixed, TInputSettings, {CIO::iNone, 0}) // Включен левый сигнал поворота +SETTING (iRightTurnLight, NotFixed, TInputSettings, {CIO::iNone, 0}) // Включен правый сигнал поворота +SETTING (iArm, NotFixed, TInputSettings, {CIO::iNone, 0}) // для подключения внешнего GSM модуля, например +SETTING (iSensorAlarm, NotFixed, TInputSettings, {CIO::iNone, 0}) // зона тревоги с внешнего Сенсора (MWS или SHOCK) +SETTING (iSensorNotify, NotFixed, TInputSettings, {CIO::iNone, 0}) // зона предупреждения с внешнего Сенсора (MWS или SHOCK) +SETTING (iEngine, NotFixed, TInputSettings, {CIO::iNone, 0}) // двигатель работает +SETTING (iLock, NotFixed, TInputSettings, {CIO::iNone, 0}) // ЦЗ заперт +SETTING (iPreHeater, NotFixed, TInputSettings, {CIO::iNone, 0}) // подогреватель +SETTING (iLowFuelLevel, NotFixed, TInputSettings, {CIO::iNone, 0}) // Датчик низкого уровня топлива +SETTING (iACC, NotFixed, TInputSettings, {CIO::iNone, 0}) // аксессуары +SETTING (iKeyIn, NotFixed, TInputSettings, {CIO::iNone, 0}) // ключ в замке (не нужен!?) +SETTING (iSpark, NotFixed, TInputSettings, {CIO::iNone, 0}) // свечи накаливания дизеля +SETTING (iDoorsLamp, NotFixed, TInputSettings, {CIO::iNone, 0}) // Плафон освещения салона +SETTING (iTrunkLamp, NotFixed, TInputSettings, {CIO::iNone, 0}) // Плафон освещения багажника +SETTING (iTrunkWindow, NotFixed, TInputSettings, {CIO::iNone, 0}) // Концевик окна багажника +SETTING (iStartStop, NotFixed, TInputSettings, {CIO::iNone, 0}) // Вход Старт/Стоп от GSM модуля, например +SETTING (iNeutral, NotFixed, TInputSettings, {CIO::iNone, 0}) // Состояние нейтрали (для РКПП) +SETTING (iLauncher, NotFixed, TInputSettings, {CIO::iNone, 0}) // Состояние внешнего/стороннего модуля Запуска +SETTING (iDisarm, NotFixed, TInputSettings, {CIO::iNone, 0}) // для подключения внешнего GSM модуля, например +SETTING (iUnTrunk, NotFixed, TInputSettings, {CIO::iNone, 0}) // уведомление об отпирании багажника +SETTING (iUnLock, NotFixed, TInputSettings, {CIO::iNone, 0}) // ЦЗ отперт + +#ifndef iFIRST +#define iFIRST iDevice1 +#endif +SETTING_ALIAS(iLAST) +SETTING_ALIAS(iOFFSET = iFIRST) +SETTING_ALIAS(iCOUNT = (iLAST-iFIRST)) + +// дырка 75..93 +SETTING_RSRV(ReservedInp = 93) +#if defined MOBICAR_3 || defined MAGICAR_X + +SETTING (oWirePolarity, NotFixed, uint32_t, 0) // битовая маска: положительная полярность выходных проводов +SETTING (iTaho, NotFixed, TInputSettings, {CIO::iBlackPink, 0}) // мультиплексор для сигнала тахометра + +#else + +SETTING_RSRV(oWirePolarity) +SETTING (iTaho, NotFixed, TInputSettings, {CIO::iNone, 0}) // мультиплексор для сигнала тахометра + +#endif + +// настройки выходов - 96..159 +// Неопределенные устройства +SETTING (oDevice1, NotFixed, uint32_t, 0) +SETTING (oDevice2, NotFixed, uint32_t, 0) +SETTING (oDevice3, NotFixed, uint32_t, 0) +SETTING (oDevice4, NotFixed, uint32_t, 0) +SETTING (oDevice5, NotFixed, uint32_t, 0) +SETTING (oDevice6, NotFixed, uint32_t, 0) +SETTING (oDevice7, NotFixed, uint32_t, 0) +SETTING (oDevice8, NotFixed, uint32_t, 0) + +#if defined MOBICAR_1_2 + +// Базовые устройства Охранной системы +SETTING (oSiren, NotFixed, uint32_t, oBIT(oBrown)) // Сирена +SETTING (oHorn, NotFixed, uint32_t, 0) // Клаксон +SETTING (oLights, NotFixed, uint32_t, oBIT(oVioletYellow)|oBIT(oVioletBrown))// Поворотники +SETTING (oLamp, NotFixed, uint32_t, 0) // Головное освещение или габариты +SETTING (oPassiveBlockage, NotFixed, uint32_t, 0) // Пассивная блокировка (когда выключена, цепь разомкнута, блокировка включена) +SETTING (oActiveBlockage, NotFixed, uint32_t, oBIT(oBlue)) // Активная блокировка (когда выключена, цепь замкнута, блокировка выключена) +SETTING (oLockDoors, NotFixed, uint32_t, oBIT(oGreen)) // Запереть все двери +SETTING (oUnlockDoors, NotFixed, uint32_t, oBIT(oYellow)) // Отпереть все двери +SETTING (oUnlockDoorDrv, NotFixed, uint32_t, 0) // Отпереть дверь водителя +SETTING (oLockTrunk, NotFixed, uint32_t, 0) // Запереть багажник +SETTING (oUnlockTrunk, NotFixed, uint32_t, 0) // Отпереть багажник +SETTING (oLockHood, NotFixed, uint32_t, 0) // Запереть Капот +SETTING (oUnLockHood, NotFixed, uint32_t, 0) // Отпереть капот +SETTING (oCloseWindows, NotFixed, uint32_t, 0) // Закрыть окна +SETTING (oPreHeaterOn, NotFixed, uint32_t, 0) // Включение предпускового подогревателя +SETTING (oPreHeaterOff, NotFixed, uint32_t, 0) // Выключение предпускового подогревателя +SETTING (oImmOn, NotFixed, uint32_t, 0) // Устройство включающее Иммобилайзер +SETTING (oImmOff, NotFixed, uint32_t, 0) // Устройство выключающее Иммобилайзер +SETTING (oService, NotFixed, uint32_t, 0) // Устройство переводящее автомобиль в Сервисный режим +SETTING (oDisarm, NotFixed, uint32_t, 0) // Устройство осуществляющее снятие с Охраны (можно использовать как выход статической блокировки) +SETTING (oArm, NotFixed, uint32_t, 0) // Устройство осуществляющее постановку под Охрану (можно использовать как выход статической блокировки) +SETTING (oAlarm, NotFixed, uint32_t, 0) // Устройство осуществляющее включение тревоги (можно использовать как выход статической блокировки) +SETTING (oAutoStart, NotFixed, uint32_t, 0) // Состояние Автозапуска +// Базовые устройства АвтоЗапуска (подменяют или имитируют присутствие водителя в автомобиле) +SETTING (oDoorWag, NotFixed, uint32_t, 0) // Устройство махающее дверью +SETTING (oIgn, NotFixed, uint32_t, oBIT(oBrownGreen)) // Включение зажигания +SETTING (oBrake, NotFixed, uint32_t, 0) // Педаль тормоза +SETTING (oKeyIn, NotFixed, uint32_t, 0) // Ключ в замке +SETTING (oAcc, NotFixed, uint32_t, oBIT(oBrownWhite)) // Аксессуары +SETTING (oBrakeControl, Fixed, uint32_t, 0) // не используется. Делать "дырку" нельзя, ломается индексация массива +SETTING (oAuxBrake, NotFixed, uint32_t, 0) // Дополнительная линия педали тормоза +SETTING (oAuxIgn, NotFixed, uint32_t, oBIT(oBrownViolet)) // Дополнительная линия зажигания +SETTING (oSSButton, NotFixed, uint32_t, 0) // Кнопка Старт/Стоп +SETTING (oImmBypass, NotFixed, uint32_t, 0) // Обходчик встроенного иммобилайзера +SETTING (oCrank, NotFixed, uint32_t, oBIT(oBrownYellow)) // Стартер +SETTING (oCrankDisable, NotFixed, uint32_t, 0) // Блокировка Стартера + +// Дополнительные +SETTING (oLockIgn, NotFixed, uint32_t, 0) // Блокировка зажигания (когда включена, зажигание заблокировано) +SETTING (oUnLockIgn, NotFixed, uint32_t, 0) // Разблокировка зажигания (когда включена, зажигание разблокировано) +SETTING (oKLine1Relay, NotFixed, uint32_t, 0) // Устройство коммутирующее KLine интерфейс +SETTING (oAux1, NotFixed, uint32_t, 0) // Доп.канал #1 +SETTING (oAux2, NotFixed, uint32_t, 0) // Доп.канал #2 +SETTING (oAux3, NotFixed, uint32_t, 0) // Доп.канал #3 +SETTING (oEmergencyBraking, NotFixed, uint32_t, 0) // Выход сигнала Экстренного торможения +SETTING (oIllumination, NotFixed, uint32_t, 0) // Выход для сигналов вежливой подсветки +SETTING (oFoldMirrors, NotFixed, uint32_t, 0) // Сложить зеркала +SETTING (oUnfoldMirrors, NotFixed, uint32_t, 0) // Разложить зеркала +SETTING (oCloseSunroof, NotFixed, uint32_t, 0) // Закрыть люк +SETTING (oMoveSunroof, NotFixed, uint32_t, 0) // Сдвинуть люк +SETTING (oHeatedSeats, NotFixed, uint32_t, 0) // Обогрев сидений +SETTING (oTriggerDoors, NotFixed, uint32_t, 0) // Триггерное управление замками дверей +SETTING (oIgnSupport, NotFixed, uint32_t, 0) // Состояние поддержки зажигания +SETTING (oArmWithoutTag, NotFixed, uint32_t, 0) // Состояние "Охрана без метки" +SETTING (oHeatedWindows, NotFixed, uint32_t, 0) // Обогрев окон +SETTING (oKLine2Relay, Fixed, uint32_t, 0) // Mobicar3: Устройство коммутирующее KLine интерфейс +SETTING (oDVR, NotFixed, uint32_t, 0) // Выход на видеорегистратор + +#elif defined MOBICAR_3 || defined MAGICAR_X + +// Базовые устройства Охранной системы +SETTING (oSiren, NotFixed, uint32_t, oBIT(oBrown)) // Сирена +SETTING (oHorn, NotFixed, uint32_t, 0) // Клаксон +SETTING (oLights, NotFixed, uint32_t, oBIT(oBrownViolet)|oBIT(oBrownWhite))// Поворотники +SETTING (oLamp, NotFixed, uint32_t, 0) // Головное освещение или габариты +SETTING (oPassiveBlockage, NotFixed, uint32_t, 0) // Пассивная блокировка (когда выключена, цепь разомкнута, блокировка включена) +SETTING (oActiveBlockage, NotFixed, uint32_t, oBIT(oBlue)) // Активная блокировка (когда выключена, цепь замкнута, блокировка выключена) +SETTING (oLockDoors, NotFixed, uint32_t, oBIT(oBrownGreen)) // Запереть все двери +SETTING (oUnlockDoors, NotFixed, uint32_t, oBIT(oBrownYellow)) // Отпереть все двери +SETTING (oUnlockDoorDrv, NotFixed, uint32_t, 0) // Отпереть дверь водителя +SETTING (oLockTrunk, NotFixed, uint32_t, 0) // Запереть багажник +SETTING (oUnlockTrunk, NotFixed, uint32_t, 0) // Отпереть багажник +SETTING (oLockHood, NotFixed, uint32_t, 0) // Запереть Капот +SETTING (oUnLockHood, NotFixed, uint32_t, 0) // Отпереть капот +SETTING (oCloseWindows, NotFixed, uint32_t, 0) // Закрыть окна +SETTING (oPreHeaterOn, NotFixed, uint32_t, 0) // Включение предпускового подогревателя +SETTING (oPreHeaterOff, NotFixed, uint32_t, 0) // Выключение предпускового подогревателя +SETTING (oImmOn, NotFixed, uint32_t, 0) // Устройство включающее Иммобилайзер +SETTING (oImmOff, NotFixed, uint32_t, 0) // Устройство выключающее Иммобилайзер +SETTING (oService, NotFixed, uint32_t, 0) // Устройство переводящее автомобиль в Сервисный режим +SETTING (oDisarm, NotFixed, uint32_t, 0) // Устройство осуществляющее снятие с Охраны (можно использовать как выход статической блокировки) +SETTING (oArm, NotFixed, uint32_t, 0) // Устройство осуществляющее постановку под Охрану (можно использовать как выход статической блокировки) +SETTING (oAlarm, NotFixed, uint32_t, 0) // Устройство осуществляющее включение тревоги (можно использовать как выход статической блокировки) +SETTING (oAutoStart, NotFixed, uint32_t, 0) // Состояние Автозапуска +// Базовые устройства АвтоЗапуска (подменяют или имитируют присутствие водителя в автомобиле) +SETTING (oDoorWag, NotFixed, uint32_t, 0) // Устройство махающее дверью +SETTING (oIgn, NotFixed, uint32_t, oBIT(oGreenRelay)) // Включение зажигания +SETTING (oBrake, NotFixed, uint32_t, 0) // Педаль тормоза +SETTING (oKeyIn, NotFixed, uint32_t, 0) // Ключ в замке +SETTING (oAcc, NotFixed, uint32_t, oBIT(oWhiteRelay)) // Аксессуары +SETTING (oBrakeControl, Fixed, uint32_t, 0) // не используется. Выкидывать нельзя, ломается адресация выходов как массива +SETTING (oAuxBrake, NotFixed, uint32_t, 0) // Дополнительная линия педали тормоза +SETTING (oAuxIgn, NotFixed, uint32_t, 0) // Дополнительная линия зажигания +SETTING (oSSButton, NotFixed, uint32_t, 0) // Кнопка Старт/Стоп +SETTING (oImmBypass, NotFixed, uint32_t, 0) // Обходчик встроенного иммобилайзера +SETTING (oCrank, NotFixed, uint32_t, oBIT(oYellowRelay)) // Стартер +SETTING (oCrankDisable, NotFixed, uint32_t, 0) // Блокировка Стартера + +// Дополнительные +SETTING (oLockIgn, NotFixed, uint32_t, 0) // Блокировка зажигания (когда включена, зажигание заблокировано) +SETTING (oUnLockIgn, NotFixed, uint32_t, 0) // Разблокировка зажигания (когда включена, зажигание разблокировано) +SETTING (oKLine1Relay, NotFixed, uint32_t, oBIT(oOrangeBreak)) // Устройство коммутирующее KLine интерфейс +SETTING (oAux1, NotFixed, uint32_t, 0) // Доп.канал #1 +SETTING (oAux2, NotFixed, uint32_t, 0) // Доп.канал #2 +SETTING (oAux3, NotFixed, uint32_t, 0) // Доп.канал #3 +SETTING (oEmergencyBraking, NotFixed, uint32_t, 0) // Выход сигнала Экстренного торможения +SETTING (oIllumination, NotFixed, uint32_t, 0) // Выход для сигналов вежливой подсветки +SETTING (oFoldMirrors, NotFixed, uint32_t, 0) // Сложить зеркала +SETTING (oUnfoldMirrors, NotFixed, uint32_t, 0) // Разложить зеркала +SETTING (oCloseSunroof, NotFixed, uint32_t, 0) // Закрыть люк +SETTING (oMoveSunroof, NotFixed, uint32_t, 0) // Сдвинуть люк +SETTING (oHeatedSeats, NotFixed, uint32_t, 0) // Обогрев сидений +SETTING (oTriggerDoors, NotFixed, uint32_t, 0) // Триггерное управление замками дверей +SETTING (oIgnSupport, NotFixed, uint32_t, 0) // Состояние поддержки зажигания +SETTING (oArmWithoutTag, NotFixed, uint32_t, 0) // Состояние "Охрана без метки" +SETTING (oHeatedWindows, NotFixed, uint32_t, 0) // Обогрев окон +SETTING (oKLine2Relay, NotFixed, uint32_t, oBIT(oPinkBreak)) // Mobicar3: Устройство коммутирующее KLine интерфейс +SETTING (oDVR, NotFixed, uint32_t, 0) // Выход на видеорегистратор + +//SETTING (oTriggerLights, NotFixed, uint32_t, 0) // Выход на триггерную кнопку включения аварийки + +#endif // outputs + +#ifndef oFIRST +#define oFIRST oDevice1 +#endif +SETTING_ALIAS(oLAST) +SETTING_ALIAS(oOFFSET = oFIRST) +SETTING_ALIAS(oCOUNT = (oLAST-oFIRST)) + +SETTING_RSRV(ReservedOutput = 159) + +// Общий принцип настройки последовательностей: +// Если выход один, либо существует возможность соединить два выхода параллельно, то +// активное значение последовательности должно быть немного (на 10-50мс) задержано по времени +// по отношению к моменту включения пассивного состояния на противоположенной последовательности. +// Например, если у последовательности выключения выхода пассивное состояние наступает через 100мс, +// то активное состояние у последовательности включения должно быть задержано на 110-150мс от начала. + +// Еще одно замечание. +// Существуют устройства, которые сами могут отключаться, например, "Замки"/"Зеркала"/"Люк"/"Багажник", +// соответственно их можно только закрыть или открыть. +// А существуют устройства, которые включаются/выключаются по команде.. такие устройства, как правило, +// с бесконечным временем работы, например, "Подогрев сидений"/"Аварийка"/"Фары" и т.п., соответственно их +// можно включить или выключить. +// Соответственно, для устройств, которые могут быть включены/выключены, используются двойные/комплементарные +// импульсные последовательности. + +// настройки последовательностей: 160..299 +SETTING (seqSirenArm, NotFixed, TSequence, {qMS( 10),5}) // Сирена: Постановка под Охрану +SETTING (seqSirenDisarm, NotFixed, TSequence, {qMS( 10),5,10,5}) // Сирена: Снятие с Охраны +SETTING (seqSirenAlarm, NotFixed, TSequence, {qMS(100),0xF0}) // Сирена: Тревога +SETTING (seqSirenWarning, NotFixed, TSequence, {qMS( 10),0xF2,10,5,10,5,10,5}) // Сирена: Внимание! +SETTING (seqSirenCaution, NotFixed, TSequence, {qMS( 10),5,5,5}) // Сирена: Предупреждение +SETTING (seqSirenNotify, NotFixed, TSequence, {qMS( 10),5}) // Сирена: Извещение +SETTING (seqSirenShockNotify, NotFixed, TSequence, {qMS( 10),0xF2,5,5,5,5,5,5}) // Сирена: Предупреждение по датчику Удара +SETTING (seqSirenService, NotFixed, TSequence, {qMS( 10),0xF2,10,5,10,5,10,5}) // Сирена: Сервисный режим +SETTING (seqSirenDisarmAfterAlarm, NotFixed, TSequence, {qMS( 10),0xF2,10,5,10,5,10,5,10,5})// Сирена: Снятие с Охраны после тревоги +SETTING (seqSirenImHere, NotFixed, TSequence, {qMS( 50),0xF2,4,4,4,4,4,4,4,4,128,0xF3})// Сирена: Поиск автомобиля на парковке +SETTING (seqSirenReserved2, NotFixed, TSequence, {qMS( 0)}) // Сирена: Резерв + +SETTING (seqHornArm, NotFixed, TSequence, {qMS( 10),3}) // Клаксон: Постановка под Охрану +SETTING (seqHornDisarm, NotFixed, TSequence, {qMS( 10),3,10,3}) // Клаксон: Снятие с Охраны +SETTING (seqHornAlarm, NotFixed, TSequence, {qMS( 10),5,10,0xF1}) // Клаксон: Тревога +SETTING (seqHornWarning, NotFixed, TSequence, {qMS( 10),0xF2,10,3,10,3,10,3}) // Клаксон: Внимание! +SETTING (seqHornCaution, NotFixed, TSequence, {qMS( 10),3,5,3}) // Клаксон: Предупреждение +SETTING (seqHornNotify, NotFixed, TSequence, {qMS( 10),3}) // Клаксон: Извещение +SETTING (seqHornShockNotify, NotFixed, TSequence, {qMS( 10),0xF2,5,3,5,3,5,3}) // Клаксон: Предупреждение по датчику Удара +SETTING (seqHornService, NotFixed, TSequence, {qMS( 10),0xF2,10,3,10,3,10,3}) // Клаксон: Сервисный режим +SETTING (seqHornDisarmAfterAlarm, NotFixed, TSequence, {qMS( 10),0xF2,10,5,10,5,10,5,10,5})// Клаксон: Снятие с Охраны после тревоги +SETTING (seqHornImHere, NotFixed, TSequence, {qMS( 50),0xF2,4,1,4,1,4,1,4,1,128,0xF3})// Клаксон: Поиск автомобиля на парковке +SETTING (seqHornReserved2, NotFixed, TSequence, {qMS( 0)}) // Клаксон: Резерв + +SETTING (seqLightsArm, NotFixed, TSequence, {qMS(100),5}) // Поворотники: Постановка под Охрану +SETTING (seqLightsDisarm, NotFixed, TSequence, {qMS(100),5,5,5}) // Поворотники: Снятие с Охраны +SETTING (seqLightsAlarm, NotFixed, TSequence, {qMS(100),5,5,0xF1}) // Поворотники: Тревога +SETTING (seqLightsWarning, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5}) // Поворотники: Внимание! +SETTING (seqLightsCaution, NotFixed, TSequence, {qMS(100),2,2,2}) // Поворотники: Предупреждение +SETTING (seqLightsNotify, NotFixed, TSequence, {qMS(100),2}) // Поворотники: Извещение +SETTING (seqLightsShockNotify, NotFixed, TSequence, {qMS(100),3}) // Поворотники: Предупреждение по датчику Удара +SETTING (seqLightsService, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5}) // Поворотники: Сервисный режим +SETTING (seqLightsDisarmAfterAlarm, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5,5,5})// Поворотники: Снятие с Охраны после тревоги +SETTING (seqLightsImHere, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,0xF3}) // Поворотники: Поиск автомобиля на парковке +SETTING (seqLightsAutoStartMode, NotFixed, TSequence, {qMS(100),0xF2,10,5,30,0xF3}) // Поворотники: Режим AutoStart +SETTING (seqLightsAutoStartOnOff, NotFixed, TSequence, {qMS(100),14}) // Поворотники: Включение/выключение режима AutoStart + +SETTING (seqLampArm, NotFixed, TSequence, {qMS(100),5}) // Фары/габариты: Постановка под Охрану +SETTING (seqLampDisarm, NotFixed, TSequence, {qMS(100),5,5,5}) // Фары/габариты: Снятие с Охраны +SETTING (seqLampAlarm, NotFixed, TSequence, {qMS(100),5,5,0xF1}) // Фары/габариты: Тревога +SETTING (seqLampWarning, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5}) // Фары/габариты: Внимание! +SETTING (seqLampCaution, NotFixed, TSequence, {qMS(100),2,2,2}) // Фары/габариты: Предупреждение +SETTING (seqLampNotify, NotFixed, TSequence, {qMS(100),2}) // Фары/габариты: Извещение +SETTING (seqLampShockNotify, NotFixed, TSequence, {qMS(100),3}) // Фары/габариты: Предупреждение по датчику Удара +SETTING (seqLampService, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5}) // Фары/габариты: Сервисный режим +SETTING (seqLampDisarmAfterAlarm, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,5,5,5,5,5})// Фары/габариты: Снятие с Охраны после тревоги +SETTING (seqLampImHere, NotFixed, TSequence, {qMS(100),0xF2,2,5,5,0xF3}) // Фары/габариты: Поиск автомобиля на парковке +SETTING (seqLampAutoStartMode, NotFixed, TSequence, {qMS(100),0xF2,10,5,30,0xF3}) // Фары/габариты: Режим AutoStart +SETTING (seqLampAutoStartOnOff, NotFixed, TSequence, {qMS(100),14}) // Фары/габариты: Включение/выключение режима AutoStart + +SETTING (seqActiveBlockageOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включить активную блокировку +SETTING (seqActiveBlockageOff, NotFixed, TSequence, {qMS( 10),0}) // Выключить активную блокировку +SETTING (seqPassiveBlockageOn, NotFixed, TSequence, {qMS( 10),0}) // Включить пассивную блокировку +SETTING (seqPassiveBlockageOff, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Выключить пассивную блокировку + +SETTING (seqLockDoors, NotFixed, TSequence, {qMS( 10),0xF2,1,50}) // Запереть центральный замок (периметр/двери) +SETTING (seqUnlockDoors, NotFixed, TSequence, {qMS( 10),0xF2,1,50}) // Отпереть центральный замок +SETTING (seqUnlockDoorDrv, NotFixed, TSequence, {qMS( 10),0xF2,1,50}) // Отпереть только дверь водителя + +SETTING (seqLockHood, NotFixed, TSequence, {qMS( 10),0xF2,1,80}) // Запереть капот +SETTING (seqUnlockHood, NotFixed, TSequence, {qMS( 10),0xF2,1,80}) // Отпереть капот +SETTING (seqUnlockHoodService, NotFixed, TSequence, {qMS(100),0xF2,25,8}) // Отпереть капот в режиме Автосервис + +SETTING (seqLockTrunk, NotFixed, TSequence, {qMS( 10),0xF2,1,50}) // Запереть багажник +SETTING (seqUnlockTrunk, NotFixed, TSequence, {qMS( 10),0xF2,1,50}) // Отпереть багажник + +SETTING (seqCloseWindows, NotFixed, TSequence, {qMS(100),200}) // Закрыть окна + +SETTING (seqPreHeaterOn, NotFixed, TSequence, {qMS(100),0xF2,1,0xF0}) // Включить предпусковой подогреватель +SETTING (seqPreHeaterOff, NotFixed, TSequence, {qMS(100),0xF2,1,10}) // Выключить предпусковой подогреватель + +SETTING (seqUnused1, NotFixed, TSequence, {qMS( 0)}) // Неиспользуется +SETTING (seqUnused2, NotFixed, TSequence, {qMS( 0)}) // Неиспользуется +SETTING (seqUnused3, NotFixed, TSequence, {qMS( 0)}) // Неиспользуется +SETTING (seqUnused4, NotFixed, TSequence, {qMS( 0)}) // Неиспользуется + +SETTING (seqImmOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включить Иммобилайзер +SETTING (seqImmOff, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Выключить Иммобилайзер + +SETTING (seqServiceOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включение +SETTING (seqServiceOff, NotFixed, TSequence, {qMS( 10),0}) // Выключение +SETTING (seqDisarmOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включение +SETTING (seqDisarmOff, NotFixed, TSequence, {qMS( 10),0}) // Выключение +SETTING (seqArmOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включение Охраны +SETTING (seqArmOff, NotFixed, TSequence, {qMS( 10),0}) // Выключение Охраны +SETTING (seqAlarmOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включение Тревоги +SETTING (seqAlarmOff, NotFixed, TSequence, {qMS( 10),0}) // Выключение Тревоги + +SETTING (seqAutoStartOn, NotFixed, TSequence, {qMS(100),0}) // Включение Автозапуска +SETTING (seqAutoStartDone, NotFixed, TSequence, {qMS(100),0}) // Успешный пуск Автозапуска +SETTING (seqAutoStartOff, NotFixed, TSequence, {qMS(100),0}) // Выключение Автозапуска + +SETTING (seqLockIgnOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включить блокировку зажигания +SETTING (seqLockIgnOff, NotFixed, TSequence, {qMS( 10),0}) // Выключить блокировку зажигания +SETTING (seqUnLockIgnOn, NotFixed, TSequence, {qMS( 10),0xF2,1,0xF0}) // Включить разблокировку зажигания +SETTING (seqUnLockIgnOff, NotFixed, TSequence, {qMS( 10),0}) // Выключить разблокировку зажигания + +SETTING (seqAux1, NotFixed, TSequence, {qMS(100),5}) // Сигнал включения Доп.канала #1 +SETTING (seqAux2, NotFixed, TSequence, {qMS(100),5}) // Сигнал включения Доп.канала #2 +SETTING (seqAux3, NotFixed, TSequence, {qMS(100),5}) // Сигнал включения Доп.канала #3 + +// Последовательности для модуля Запуска +SETTING (seqDoorWag, NotFixed, TSequence, {qMS(100),0xF2,5,5,5}) // Махнуть дверью: пауза для некоторых тормозных НИССАНов (Демин/Семибратов просили добавить) +SETTING (seqImmByOff, NotFixed, TSequence, {qMS(100),6}) // Обходчик иммобилайзера: выключить +SETTING (seqImmByOn, NotFixed, TSequence, {qMS(100),0xF2,1,0xF0}) // Обходчик иммобилайзера: включить +SETTING (seqKeyInOff, NotFixed, TSequence, {qMS(100),5}) // Ключ в замке: выключить +SETTING (seqKeyInOn, NotFixed, TSequence, {qMS(100),0xF2,2,0xF0}) // Ключ в замке: включить +SETTING (seqAccOff, NotFixed, TSequence, {qMS(100),4}) // Аксессуары: выключить +SETTING (seqAccOn, NotFixed, TSequence, {qMS(100),0xF2,3,0xF0}) // Аксессуары: включить +SETTING (seqIgnOff, NotFixed, TSequence, {qMS(100),3}) // Зажигание 1: выключить +SETTING (seqIgnOn, NotFixed, TSequence, {qMS(100),0xF2,5,0xF0}) // Зажигание 1: включить +SETTING (seqBrakeOff, NotFixed, TSequence, {qMS(100),2}) // Педаль тормоза: выключить +SETTING (seqBrakeOn, NotFixed, TSequence, {qMS(100),0xF2,5,0xF0}) // Педаль тормоза: включить +SETTING (seqCrankOn, NotFixed, TSequence, {qMS(100),0xF2,10,30}) // Стартер: включить +SETTING (seqCrankDisableOff, NotFixed, TSequence, {qMS(100),7}) // Блокировка стартера: выключить +SETTING (seqCrankDisableOn, NotFixed, TSequence, {qMS(100),0xF0}) // Блокировка стартера: включить +SETTING (seqAuxIgnOff, NotFixed, TSequence, {qMS(100),3}) // Зажигание 2: выключить +SETTING (seqAuxIgnOn, NotFixed, TSequence, {qMS(100),0xF2,5,0xF0}) // Зажигание 2: включить +SETTING (seqAuxBrakeOff, NotFixed, TSequence, {qMS(100),1}) // Педаль тормоза 2: выключить +SETTING (seqAuxBrakeOn, NotFixed, TSequence, {qMS(100),0xF2,6,0xF0}) // Педаль тормоза 2: включить +SETTING (seqPrestartSSB, NotFixed, TSequence, {qMS(100),0xF2,10,6}) // Первое нажатие на SSB в SetPRESTART +SETTING (seqCrankSSB, NotFixed, TSequence, {qMS(100),0xF2,10,30}) // Нажатие на SSB во время CRANK +SETTING (seqStopSSB, NotFixed, TSequence, {qMS(100),0xF2,21,6}) // Первое нажатие на SSB в SetSTOP, при неавтоматическом подборе нажатий! (пауза в начале для учета параллельных процессов связанных с окончанием, например, включение/выключение обходчика и др.) +SETTING (seqPressSSB, NotFixed, TSequence, {qMS(100),0xF2,10,6}) // Сигнал дополнительных/повторных нажатий на SSB (PRESTART/STOP) + +SETTING (seqEmergencyBraking, NotFixed, TSequence, {qMS(100),0xF2,5,5,0xF2}) // Сигнал экстренного торможения +SETTING (seqIllumination, NotFixed, TSequence, {qMS(100),20,0xF3,10,0xF5,20,0xF7,20,0xF9,20,0xFB,20,0xFD,20,0xFF,20})// Сигнал вежливой подсветки +SETTING (seqFoldMirrors, NotFixed, TSequence, {qMS(100),0}) // Сложить зеркала +SETTING (seqUnfoldMirrors, NotFixed, TSequence, {qMS(100),0}) // Разложить зеркала +SETTING (seqCloseSunroof, NotFixed, TSequence, {qMS(100),0}) // Закрыть люк +SETTING (seqMoveSunroof, NotFixed, TSequence, {qMS(100),0}) // Сдвинуть люк + +SETTING (seqShockAlarmTestMode, NotFixed, TSequence, {qMS( 10),0xF2,5,50}) // Сигнал тревоги по датчику удара в режиме настройки +SETTING (seqHeatedSeatsOn, NotFixed, TSequence, {qMS(100),0}) // Включение подогрева сидений +SETTING (seqHeatedSeatsOff, NotFixed, TSequence, {qMS(100),0}) // Выключение подогрева сидений + +SETTING (seqIgnSupportOn, NotFixed, TSequence, {qMS(100),0xF0}) // Статус включение поддержки зажигания +SETTING (seqIgnSupportOff, NotFixed, TSequence, {qMS(100),0}) // Статус выключение поддержки зажигания + +SETTING (seqArmWithoutTagOn, NotFixed, TSequence, {qMS(100),0xF2,10,0xF0}) // Включение состояния "Охрана без метки" +SETTING (seqArmWithoutTagOff, NotFixed, TSequence, {qMS(100),0}) // Выключение состояния "Охрана без метки" + +SETTING (seqHeatedWindowsOn, NotFixed, TSequence, {qMS(100),0}) // Включение подогрева окон +SETTING (seqHeatedWindowsOff, NotFixed, TSequence, {qMS(100),0}) // Выключение подогрева окон + +//SETTING (seqTriggerStart, NotFixed, TSequence, {qMS(100),30}) // Сигнал первого нажатия на триггерную кнопку +//SETTING (seqTriggerNext, NotFixed, TSequence, {qMS( 10),10,10}) // Сигнал всех последующих нажатий на триггерную кнопку + +#ifndef seqFIRST // последовательности ядра +#define seqFIRST seqSirenArm +#endif +SETTING_ALIAS(seqHOLE) + +SETTING_RSRV(seqProgs = 283) +// Шаблоны CAN прошивки (обезличиненные, приобретают смысл в CAN прошивке) +// В Universe, доп. импульсные последовательности используются максимум 4ре штуки... +// Поэтому, при нехватке последователльностей, можно "откусывать" от программируемых. +SETTING (seqProg16, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg15, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg14, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg13, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg12, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg11, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg10, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg9, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg8, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg7, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg6, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg5, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg4, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg3, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg2, NotFixed, TSequence, {qMS( 0)}) +SETTING (seqProg1, NotFixed, TSequence, {qMS( 0)}) + +SETTING_ALIAS(seqOFFSET = seqFIRST) +SETTING_ALIAS(seqCOUNT = (seqProg1+1-seqFIRST)) +SETTING_RSRV(seqLAST = 299) + +// прочие системные настройки: 300 +SETTING (KeyAES, NotFixed, TKeyAES, {0}) // ключ шифрования +SETTING (Kxx, NotFixed, uint16_t, 37) // ~690RPM // Калибровочный коэф. холостого хода +SETTING (VIN, NotFixed, TVehicleID, {0}) // VIN-код авто +SETTING (ImmoKeyArr, NotFixed, TImmoKey, {0}) // Ключ обходчика иммобилайзера +SETTING_RSRV(BrelokCount) // Количество подшитых брелков X1/X2 +SETTING (ImmoKeyAuxArr, NotFixed, TImmoKey, {0}) // Расширение ключа обходчика иммобилайзера (дополнительное поле) + +SETTING_RSRV(LastSystemSettings = 0x013F) // 319 + +// настройки индикации светом: 0x0140 (320) +SETTING (LightsArm, NotFixed, bit_t, 1) // при включении охраны +SETTING (LightsDisarm, NotFixed, bit_t, 1) // при выключении охраны +SETTING (LightsAlarm, NotFixed, bit_t, 1) // при тревоге +SETTING (LightsTrunkLock, NotFixed, bit_t, 0) // при запирании багажника +SETTING (LightsAutoStartMode, NotFixed, uint8_t, defLightsAutoStartMode) // режим работы световой индикации при автозапуске: 0=OFF; 1=при вкл/выкл Автозапуска; 2=..и во время Автозапуска +SETTING_RSRV(AutoStartLightsAlwaysOn) // при работе автозапуска +SETTING_RSRV(LightsAutoStartOff) // при выключении автозапуска +SETTING_RSRV(LightsAuxChannelOn) // при включении дополнительного канала +SETTING (IlluminationMode, NotFixed, uint8_t, defIlluminationMode) // режим включения вежливой подсветки: 0=OFF; 1=Arm; 2=Disarm; 3=Arm+Disarm. +SETTING_RSRV(IndLightIllumDuration) // вежливая подсветка, длительность +SETTING (LightsShockNotify, NotFixed, bit_t, 1) // при срабатывании предупреждения датчика удара +SETTING_RSRV(LightsSelfArming) // предупреждение об автопостановке +SETTING_RSRV(_EmergencyBraking) // выдавать сигнал об экстренном торможении +SETTING_RSRV(LightsHiJackOff) // при выходе из хайджека +SETTING_RSRV(LightsImmoOff) // при выходе из иммобилайзера +SETTING_RSRV(LightsNoReservation) // не выполнена подготовка к автозапуску +SETTING_RSRV(LightsHeadLampOn) // не выключены фары + +SETTING_RSRV(IndLightReserved = 0x015F) + +// настройки индикации сиреной: 0x0160 (352) +SETTING (SoundArm, NotFixed, bit_t, 1) // при включении охраны +SETTING (SoundDisarm, NotFixed, bit_t, 1) // при выключении охраны +SETTING (SoundsDisable, NotFixed, bit_t, 0) // отключение всех звуков: тревога/подтверждения +SETTING_RSRV(SoundAutoStartOn) // при включении автозапуска +SETTING_RSRV(SoundAutoStartMode) // при остатке времени автозапуска 2 минуты +SETTING_RSRV(SoundAutoStartOff) // при выключении автозапуска +SETTING_RSRV(SoundAuxChannelOn) // при включении дополнительного канала +SETTING_RSRV(SoundShockNotify) // при срабатывании предупреждения датчика удара +SETTING_RSRV(SoundHeadLampOn) // не выключены фары +SETTING_RSRV(SoundSelfArming) // предупреждение об автопостановке +SETTING_RSRV(SoundHiJackOff) // при выходе из режима хайджек +SETTING_RSRV(SoundServiceNotify) // напоминание о необходимости выйти из режима Автосервис +SETTING_RSRV(SoundImmoOff) // при выходе из режима иммобилайзера +SETTING_RSRV(SoundNoReservation) // не выполнена подготовка к автозапуску +SETTING (SoundsNoticesDisable, NotFixed, bit_t, 0) // Отключить все звуки уведомлений + +SETTING_RSRV(SoundsReserved = 0x017F) + +// настройки центрального замка: 0x0180 (384) +SETTING_RSRV(LockOnAutoArm) // запирание при автопостановке +SETTING_RSRV(LockOnArmReturn) // запирание при возврате в охрану +SETTING (LockByDriveMode, NotFixed, uint8_t, defLockByDriveMode) // режим запирания ЦЗ: нет / по педали тормоза / по началу движения / по включению зажигания +SETTING (LockOnAutostartBegin, NotFixed, bit_t, 0) // запирание при начале автозапуска +SETTING (LockOnAutostartEnd, NotFixed, bit_t, 0) // запирание по окончанию автозапуска +SETTING (LockOnAlarmEnd, NotFixed, bit_t, 0) // запирание при выходе из тревоги +SETTING (LockOnTrunkClose, NotFixed, bit_t, 0) // запирание по завершению процедуры открытия багажника в Охране +SETTING (UnlockByParkMode, NotFixed, uint8_t, defUnlockByParkMode)// отпирание при выключении зажигания +SETTING_RSRV(UnlockByEmergencyBraking) // отпирание при экстренном торможении +SETTING (UnlockPriority, NotFixed, bit_t, 0) // приоритетное отпирание замков +SETTING (DriveDoorsAutostart, NotFixed, bit_t, 0) // Управлять замками дверей по SlaveArm/SlaveDisarm в режиме Автозапуска + +SETTING_RSRV(LockReserved = 0x019F) + +// настройки режимов "охрана", "снято с охраны": 0x01A0 (416) +SETTING_RSRV(ArmAuto) // автопостановка при закрытии дверей, нет / по закрытию дверей / по отсутствию метки +SETTING_RSRV(ArmAutoTimeout) // таймаут автопостановки +SETTING (Comfort, NotFixed, uint8_t, 1) // управление функциями "комфорта": зеркала, стекла, люк +SETTING (ArmReturnTimeIndex, NotFixed, uint8_t, defArmReturnTimeIndex) // индекс массива времен автоматической перепостановки +SETTING (PlafondAlarmDelay, NotFixed, uint8_t, defPlafondAlarmDelay) // время блокировки тревог от сигналов освещения багажника и салона +SETTING (DoorsLampDeciseconds, NotFixed, uint8_t, defDoorsLampDeciseconds)// таймер отсрочки выключенного состояния плафона освещения салона +SETTING (TrunkLampDeciseconds, NotFixed, uint8_t, defTrunkLampDeciseconds)// таймер отсрочки выключенного состояния плафона освещения багажника +SETTING (HandsfreeMode, NotFixed, uint8_t, 0) // постановка/снятие при появлении телефона-метки: бит 0 - автопостановка, бит 1 - автоснятие +SETTING (DisarmWithTagOnly, NotFixed, bit_t, 0) // снятие с охраны только при наличии телефона-метки, прерывание тревоги не запрещает +SETTING (DriveBuiltinSystem, NotFixed, bit_t, 1) // управлять штатной системой авто +SETTING (SlaveModeEnable, NotFixed, bit_t, 0) // управление от штатной системы +SETTING (SlaveComfort, NotFixed, bit_t, 0) // управлять комфортом при постановке в Охрану по SLAVE. +SETTING (DisarmEmergPinVal, NotFixed, uint16_t, 1111) // ПИН-код для аварийного снятия с охраны +SETTING_RSRV(ArmAutoReadyNote) // предупреждение о готовности к автопостановке +SETTING (SlaveDisarmWithTagOnly,NotFixed, bit_t, 0) // снятие с охраны по SLAVE-входу только при наличии телефона-метки, прерывание тревоги не запрещает + +SETTING_RSRV(ArmReserved = 0x01BF) + +// настройки режима "тревога": 0x01C0 (448) +SETTING (AlarmDoorsDeciseconds, NotFixed, uint8_t, defAlarmDoorsDeciseconds) // Задержка тревоги по входам дверей (*100мс) +SETTING (AlarmTrunkDeciseconds, NotFixed, uint8_t, defAlarmTrunkDeciseconds) // Задержка тревоги по входам багажника (*100мс) +SETTING (KillEngineDeciseconds, Fixed, uint8_t, defKillEngineDeciseconds) // Период выдачи команды : 0:Single; >127:OFF.. + +SETTING_RSRV(AlarmReserved = 0x01DF) + +// настройки режима "хайджек" и работы с Меткой: 0x01E0 (480) +SETTING_RSRV(TagsRSSI) // Значения уровней RSSI метки для Автопостановки/Автоснятия + +SETTING_RSRV(HijackReserved = 0x01FF) + +// настройки режима "иммобилайзер": 0x0200 (512) +SETTING (Immobilizer, NotFixed, bit_t, 0) // функция иммобилайзер + +SETTING_RSRV(ImmoReserved = 0x021F) + +// настройки режима "автосервис": 0x0220 (544) +// не используются + +SETTING_RSRV(ServiceReserved = 0x023F) + +// настройки автозапуска: 0x0240 (576) +SETTING (TurboTimerIndex, NotFixed, uint8_t, defTurboTimerIndex) // индекс массива настроек турботаймера: 0=Off, 1=On, 2=Auto +SETTING (ReadyMinutes, NotFixed, uint8_t, defReadyMinutes) // длительность режима READY, в минутах +SETTING (SupportMinutes, NotFixed, uint8_t, defSupportMinutes) // длительность режима SUPPORT, в минутах +SETTING (PitStopTimeIndex, NotFixed, uint8_t, defPitStopTimeIndex)// индекс массива длительностей режима PITSTOP +SETTING (PreHeaterMinutes, NotFixed, uint8_t, defPreHeaterMinutes)// длительность работы PreHeater, в минутах +SETTING (SSB, NotFixed, bit_t, 0) // StartStopButton +SETTING_RSRV(WakeUpBySSB)//, NotFixed, bit_t, 0) // Будить автомобиль нажатием на кнопку SSB +SETTING (SetReadyMode, NotFixed, uint8_t, defSetReadyMode) // режим включения поддержки зажигания +SETTING (SkipPreStartMode, Fixed, bit_t, 0) // сразу же (без проверки статусов автомобиля) запустить двигатель - только для SSB! +SETTING (PowerStart, NotFixed, bit_t, 0) // запуск автомобиля с SSB по силе - только для SSB! +SETTING (ManualAttempts, NotFixed, uint8_t, defManualAttempts) // кол-во попыток запуска по команде с Брелока +SETTING (ReadyDisableImmBypass, NotFixed, bit_t, 1) // запрет включения обходчика при включении поддержки +SETTING (CrankAuxIgnOff, NotFixed, bit_t, 1) // выключать выход во время работы +SETTING (SupportImmBypassOff, NotFixed, bit_t, 1) // выключать обходчик после успешного пуска двигателя +SETTING (StopByDisarm, NotFixed, bit_t, 0) // глушить при снятии с охраны +SETTING (ClrReadyMode, NotFixed, uint8_t, defClrReadyMode) // режим выключения поддержки зажигания +SETTING (AutostartShockEnable, NotFixed, bit_t, 0) // разрешение тревоги по датчику удара в режимах Автозапуска +SETTING (PrestartSSB, NotFixed, uint8_t, defPrestartSSB) // Максимальное кол-во нажатий на SSB в PRESTART: 0-по умолчанию +SETTING (StopSSB, NotFixed, uint8_t, defStopSSB) // Максимальное кол-во нажатий на SSB в STOP: 0-по умолчанию +SETTING (CrankDelaySeconds, NotFixed, uint8_t, defCrankDelaySeconds) // Задержка перед включением стартера, в секундах +SETTING (AutostartBatteryLevel, NotFixed, uint8_t, defAutoStartBatteryLevel) // автозапуск при разряде аккумулятора (десятые доли вольта) +SETTING (AutostartTemperature, NotFixed, int8_t, defAutoStartTemperature) // автозапуск по температуре салона +SETTING_RSRV(MorningRun) // утренний запуск +SETTING_RSRV(EveningRun) // вечерний запуск +SETTING (DailyRunCountIndex, NotFixed, uint8_t, defDailyRunCountIndex) // индекс массива настроек кол-ва суток действия таймерных запусков: бесконечность<0, отключить все таймерные запуски=0. +SETTING (AutomaticsPeriodIndex, NotFixed, uint8_t, defAutomaticsPeriodIndex) // индекс массива настроек таймеров блокировки автоматических запусков +SETTING (AutomaticsLimitIndex, NotFixed, uint8_t, defAutomaticsLimitIndex) // индекс массива настроек ограничителей автоматических запусков за сессию Охраны +SETTING (EngineStartPercent, NotFixed, uint8_t, defEngineStartPercent) // процент от ХХ*2 для детектора состояния запущенного двигателя +SETTING (EngineRunPercent, NotFixed, uint8_t, defEngineRunPercent) // процент от ХХ*2 для детектора состояния работающего двигателя +SETTING (TurboTimerPercent, NotFixed, uint8_t, defTurboTimerPercent) // процент от ХХ*2 для детектора состояния работающего двигателя +SETTING (TimerRun0, NotFixed, TStartTimerSetting, {0x8000, 0}) // таймерный запуск +SETTING (TimerRun1, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun2, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun3, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun4, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun5, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun6, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun7, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun8, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun9, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun10, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun11, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun12, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (TimerRun13, NotFixed, TStartTimerSetting, {0x8000, 0}) +SETTING (SlaveStartStop, NotFixed, bit_t, 1) // Запуск/Останов двигателя по SLAVE команде со штатного брелока +SETTING (ExternalHeatersEnable, NotFixed, bit_t, 1) // разрешение управлять внешними нагревателями +SETTING (ExternalHeatersTemperature,NotFixed, int8_t, defExternalHeatersTemperature) // пороговая температура включения нагревателя +SETTING (ExternalTemperatureSensorType,NotFixed,uint8_t, 0) // Тип внешнего датчика температуры (0=SEMITEC 103AT-2; 1=MF52A103J3950) + +SETTING_RSRV(AutoStartReserved = 0x027F) + +// настройки обработчика Акселерометра: 0x0280 (640) +SETTING (ShockNotify, NotFixed, uint8_t, 6) // чувствительность предупреждения по датчику Удара [2..9] +SETTING (ShockAlarm, NotFixed, uint8_t, 5) // чувствительность тревоги по датчику Удара [1..8] +SETTING (TiltAlarm, NotFixed, uint8_t, 5) // чувствительность тревоги по датчику Наклона [1..9] +SETTING (MotionAlarm, NotFixed, uint8_t, 5) // чувствительность тревоги по датчику Передвижения/Перемещения [1..9] +SETTING (EmergencyBraking, NotFixed, uint8_t, defEmergencyBraking) // 0-ничего не делать; 1-только моргать; 2-моргать и отпиреть ЦЗ; +// Формат вышеуказанных полей состоит в том, что старший бит - это флажок Disable. +// Т.е. если он стоит, то датчик с указанным уровнем чувствительности выключен. +SETTING (ShockSensTable, NotFixed, uint8_t, 0) // Индекс таблицы чувствительностей (варианты шкал чувствительностей) +//SETTING_ALIAS(AccelSTART = ShockNotify) +SETTING_RSRV(AccelLAST = 0x029F) + +#ifdef MOBICAR_3 + +// настройки Абонентских оповещений: 0x02A0 (672) +SETTING_RSRV(PhoneNumber1) // телефонный номер 1го абонента +SETTING_RSRV(PhoneNumber2) // телефонный номер 2го абонента +SETTING_RSRV(PhoneNumber3) // телефонный номер 3го абонента +SETTING_RSRV(PhoneNumber4) // телефонный номер 4го абонента + +SETTING_RSRV(SMS1) // SMS оповещения 1го абонента +SETTING_RSRV(SMS2) // SMS оповещения 2го абонента +SETTING_RSRV(SMS3) // SMS оповещения 3го абонента +SETTING_RSRV(SMS4) // SMS оповещения 4го абонента + +SETTING_RSRV(Call1) // Голосовые оповещения 1го абонента +SETTING_RSRV(Call2) // Голосовые оповещения 2го абонента +SETTING_RSRV(Call3) // Голосовые оповещения 3го абонента +SETTING_RSRV(Call4) // Голосовые оповещения 4го абонента + +SETTING_RSRV(SubscriberNotifications = 0x02AF) + +// настройки Модема: 0x02B0 (688) +SETTING_RSRV(USSD) // USSD запрос +SETTING_RSRV(VoiceRoamEnable) // разрешены голосовые оповещения в роуминге +SETTING_RSRV(DataRoamEnable) // разрешена передача данных по GPRS в роуминге +SETTING_RSRV(SMSRoamEnable) // разрешена отправка SMS в роуминге +SETTING_RSRV(WaitAnswerTimeout) // время ожидания ответа абонента при оповещении, сек +SETTING_RSRV(CallEndTimeout) // таймаут окончания звонка при бездействии абонента, сек +SETTING_RSRV(TripEndTimeout) // таймаут окончания поездки при выключении зажигания, сек +SETTING_RSRV(LowBatteryVoltage) // уровень входного напряжения генерации оповещения (десятые доли вольта) + +SETTING_RSRV(ModemBaseOptions = 0x02BF) + +// настройки Модема расширенные: 0x02C0 (704) +SETTING_RSRV(ParkingLocRequest) // определять место парковки по БС +SETTING_RSRV(TripLocTimeout) // интервал запроса информации по БС во время поездки, *10сек (=0 не определять) +SETTING_RSRV(EvacLocTimeout) // интервал запроса информации по БС во время эвакуации, *10сек (=0 не определять) +SETTING_RSRV(SMSLoc) // добавлять координаты в SMS +SETTING_RSRV(TimeZone) // Часовой пояс, в часах +SETTING_RSRV(Internet) // признак версии PRO (соединение по Internet) +SETTING_RSRV(ModemAPN) // Строка APN +SETTING_RSRV(ModemLogin) // Строка Login +SETTING_RSRV(ModemPassword) // Строка Password +SETTING_RSRV(DTCRequestTimeout) // интервал времени после выключения зажигания для запроса DTC, *1сек (=0 не определять) +SETTING_RSRV(ClockSyncMode) // Режим синхронизации Системных часов: 0=OFF, 1=PhoneClock, 2=NetworkClock +SETTING_RSRV(TimeZoneSyncMode) // Режим синхронизации Системной зоны: 0=OFF, 1=PhoneTimeZone, 2=NetworkTimeZone + +#endif + +SETTING_RSRV(ModemExtOptions = 0x02CF) + +SETTING_RSRV(CoreReserved = 0x05EF) + +// настройки 0x5F0 .. 0x5FF - настройки ядра под CAN-прошивку +SETTING (iCanAvail_Mask, Fixed, uint32_t, 0) // входы, доступные в CAN-прошивке, битовая маска +SETTING (oCanAvail_Mask, Fixed, uint64_t, 0) // выходы, доступные в CAN-прошивке, битовая маска +SETTING (valCanAvail_Mask, Fixed, uint32_t, 0) // числовые значения, доступные в CAN-прошивке, битовая маска +SETTING (valCanEn_Mask, NotFixed, uint32_t, 0) // используемые числовые значения из CAN-прошивки, битовая маска + +#undef SETTING +#undef SETTING_RSRV +#undef SETTING_ALIAS diff --git a/libs/SysTimer.h b/libs/SysTimer.h new file mode 100644 index 0000000..f87cc34 --- /dev/null +++ b/libs/SysTimer.h @@ -0,0 +1,83 @@ +#ifndef SYSTIMER_H +#define SYSTIMER_H + +#include +#include "CanFwInterface.h" + +// миллисекундный таймер. Макс. таймаут - 2**32 мс. + +class TimerMs { +public: + typedef uint32_t T_Timer; + + TimerMs() + { Restart(); } + virtual ~TimerMs() + { } + + virtual inline T_Timer Restart(void) + { + auto prev = _tmr; + _tmr = CntValue(); + return _tmr - prev; + } + + inline T_Timer Value(void) const + { return CntValue() - _tmr; } + + inline T_Timer Rest(const T_Timer timeout) const + { + T_Timer elapsed = Value(); + if (elapsed < timeout) + return timeout - elapsed; + return 0; + } + + inline bool CheckTimeout(const T_Timer timeout) const + { return Value() > timeout; } + +private: + T_Timer _tmr; + + static inline T_Timer CntValue(void) + { return CoreFunc->GetTickMs(); } + +}; + +class TimerMsOnce : public TimerMs +{ +public: + TimerMsOnce() : TimerMs() + { started = true; } + virtual ~TimerMsOnce() + { } + + virtual inline T_Timer Restart(void) + { + auto elapsed = TimerMs::Restart(); + started = true; + return elapsed; + } + + inline bool IsStarted(void) const + { return started; } + + inline void Stop(void) + { started = false; } + + virtual inline bool CheckTimeout(T_Timer timeout) + { + if (started) + { + if (Value() <= timeout) + return false; + Stop(); + } + return true; + } + +private: + bool started; +}; + +#endif // SYSTIMER_H diff --git a/libs/Utils.h b/libs/Utils.h new file mode 100644 index 0000000..57e1dd8 --- /dev/null +++ b/libs/Utils.h @@ -0,0 +1,73 @@ +/* + * Utils.h + * + * Created on: 29 мая 2015 г. + * Author: esaulenko + */ + +#ifndef UTILS_H_ +#define UTILS_H_ + + +#include +#include "IO.h" + + +uint32_t constexpr BIT (uint32_t n) +{ return 1UL << n; } + +uint64_t constexpr BIT64 (uint32_t n) +{ return 1ULL << n; } + +template uint32_t MAX (T1 a, T2 b) +{ + if (a > b) return a; + else return b; +} + +template uint32_t MIN (T1 a, T2 b) +{ + if (a > b) return b; + else return a; +} + + + + +#define countof(array) (sizeof(array)/sizeof(array[0])) + + + +// установка/снятие бита + +template void BSET (T &x, uint32_t bitNo) ///< установить бит +{ x |= BIT64 (bitNo); } + +template void BCLR (T &x, uint32_t bitNo) ///< стереть бит +{ x &= ~BIT64 (bitNo); } + +///< определить (стереть (Value=0) или установить(Value=1)) бит +template void BDEF (T &x, uint32_t bitNo, uint32_t Value) +{ + if (Value) BSET (x, bitNo); + else BCLR (x, bitNo); +} + + + +// возвращает номер старшего бита +constexpr int8_t bitmask2offset (uint32_t val) +{ + return (int8_t) ( (val > 1) ? ( bitmask2offset (val/2) + 1 ) : 0 ); +} + + + +// управление последовательностями +// использовать в CoreFunc->RunSequence() +#define SEQ(x,y) CIO::x, CSettings::y-CSettings::seqOFFSET + + + + +#endif /* UTILS_H_ */ diff --git a/libs/WeakFunc.cpp b/libs/WeakFunc.cpp new file mode 100644 index 0000000..5410835 --- /dev/null +++ b/libs/WeakFunc.cpp @@ -0,0 +1,40 @@ +#include "source/SourcePath.h" +#include SRC_HEADER + +// функции-пустышки + +// инициализирует ОЗУ, вызывается при старте контроллера +__attribute__((weak)) void Init (TCanFwMem * vars) { } + +// Вызывается при изменении настроек (на каждую настройку) +__attribute__((weak)) void SettingChanged (TCanFwMem * vars, uint16_t id) { } + +// принимает и обрабатывает пакет из CAN +__attribute__((weak)) void Can1Received (TCanFwMem * vars, TCanPkt *apPkt) { } +__attribute__((weak)) void Can2Received (TCanFwMem * vars, TCanPkt *apPkt) { } + +// обрабатывает события изменения входов-выходов +__attribute__((weak)) void InputChanged (TCanFwMem * vars, uint32_t aInputNum, bool aSwitchedOn) { } +__attribute__((weak)) void OutputChanged (TCanFwMem * vars, uint32_t aOutputNum, bool aSwitchedOn) { } +__attribute__((weak)) void GuardEvent (TCanFwMem * vars, TGuardEvents aEvent) { } + +// события начала и конца последовательностей +__attribute__((weak)) void SequenceStart (TCanFwMem * vars, uint32_t aEvent) { } +__attribute__((weak)) void SequenceStop (TCanFwMem * vars, uint32_t aEvent) { } + +// команда от ядра +__attribute__((weak)) void Command (TCanFwMem * vars, TCanFwCommands aCmd, uint32_t aCmdParam) { } + +// вызывается по таймауту +__attribute__((weak)) void PeriodicProcess (TCanFwMem * vars) { } + +// LIN +__attribute__((weak)) void Lin1Received (TCanFwMem * vars, TLinFrame *apFrame) { } +__attribute__((weak)) void Lin2Received (TCanFwMem * vars, TLinFrame *apFrame) { } +__attribute__((weak)) void Lin1Transmitted (TCanFwMem * vars, uint8_t aFrameId) { } +__attribute__((weak)) void Lin2Transmitted (TCanFwMem * vars, uint8_t aFrameId) { } +// Mobicar3 LIN +__attribute__((weak)) void Lin3Received (TCanFwMem * vars, TLinFrame *apFrame) { } +__attribute__((weak)) void Lin3Transmitted (TCanFwMem * vars, uint8_t aFrameId) { } + + diff --git a/src/CAN_FW.h b/src/CAN_FW.h new file mode 100644 index 0000000..b83a97b --- /dev/null +++ b/src/CAN_FW.h @@ -0,0 +1,17 @@ +#ifndef CAN_FW_H_ +#define CAN_FW_H_ + +#include "Settings.h" +#include "Buffer.h" +#include "Periodic.h" +#include "Can.h" + +#define CAN_FW_DESCRIPTION "Test" + +// структура с пользовательскими переменными +struct TCanFwMem { + CSettings::TSettings Settings; // структура с настройками - должна быть всегда в начале + +}; + +#endif /* CAN_FW_H_ */ diff --git a/src/CAN_Inputs.h b/src/CAN_Inputs.h new file mode 100644 index 0000000..7755ff4 --- /dev/null +++ b/src/CAN_Inputs.h @@ -0,0 +1,22 @@ +#include "CAN_FW.h" +#include "Can.h" +#include "IO.h" +#include "Utils.h" + + +void Init (TCanFwMem * vars) +{ + CoreFunc->DebugConsole("CAN_FW version: %s\n", (const char*)(gCanFwInfo.TextInfo)); + + static const TCanInit can1_init = + { + CCan::CanBaudrate500, + 1, + { + CCan::Filter::List11 (0x660), + CCan::Filter::Mask11 (0x7E0, 0x7F0), // 0x7E0..0x7EF + } + }; + CoreFunc->CanInit (CANch1, &can1_init); + +} \ No newline at end of file diff --git a/src/CAN_Outputs.h b/src/CAN_Outputs.h new file mode 100644 index 0000000..cce6be2 --- /dev/null +++ b/src/CAN_Outputs.h @@ -0,0 +1,5 @@ +#include "CAN_FW.h" +#include "Can.h" +#include "IO.h" +#include "Utils.h" + diff --git a/src/SettingsCANTable.h b/src/SettingsCANTable.h new file mode 100644 index 0000000..6739ada --- /dev/null +++ b/src/SettingsCANTable.h @@ -0,0 +1,98 @@ +//===================================================================================== + +// SETTING_RSRV позволяет сделать "дырки" в номерах настроек +// если не определена, значит, она не используется +#ifndef SETTING_RSRV +#define SETTING_RSRV(name) +#endif + +//************************** Динамические параметры ***********************************************// + +// числовые значения, доступные в CAN-прошивке, битовая маска +SETTING (valCanAvail_Mask, Fixed, uint32_t, \ + BIT(CanData_RPM) | BIT(CanData_Speed) | BIT(CanData_Odometer) | BIT(CanData_Accelerator) | \ + BIT(CanData_BrakeForce) | BIT(CanData_WheelAngle) | BIT(CanData_FuelLevel) | BIT(CanData_FuelConsumption) | + BIT(CanData_CoolantTemp) ) + +// используемые числовые значения из CAN-прошивки, битовая маска +SETTING (valCanEn_Mask, NotFixed, uint32_t, \ + BIT(CanData_RPM) | BIT(CanData_Speed) | BIT(CanData_Odometer) | BIT(CanData_Accelerator) | \ + BIT(CanData_BrakeForce) | BIT(CanData_WheelAngle) | BIT(CanData_FuelLevel) | BIT(CanData_FuelConsumption) | + BIT(CanData_CoolantTemp) ) + + +//************************** ВХОДЫ ****************************************************************// + SETTING (iDoorDrv, NotFixed, TInputSettings, {CIO::iCAN}) // Дверь водителя + SETTING (iDoorFP, NotFixed, TInputSettings, {CIO::iCAN}) // Дверь пассажира + SETTING (iDoorRL, NotFixed, TInputSettings, {CIO::iCAN}) // Дверь задняя левая + SETTING (iDoorRR, NotFixed, TInputSettings, {CIO::iCAN}) // Дверь задняя правая + SETTING (iTrunk, NotFixed, TInputSettings, {CIO::iCAN}) // Багажник + SETTING (iACC, NotFixed, TInputSettings, {CIO::iCAN}) // + SETTING (iIgn, NotFixed, TInputSettings, {CIO::iCAN}) // Зажигание + SETTING (iBrake, NotFixed, TInputSettings, {CIO::iCAN}) // Педаль тормоза + SETTING (iHBrake, NotFixed, TInputSettings, {CIO::iCAN}) // Стояночный тормоз + SETTING (iPark, NotFixed, TInputSettings, {CIO::iCAN}) // АКПП в положении "Park" + SETTING (iLock, NotFixed, TInputSettings, {CIO::iCAN}) // Замки дверей + SETTING (iLamp, NotFixed, TInputSettings, {CIO::iCAN}) // Габариты / фары + SETTING (iLeftTurnLight, NotFixed, TInputSettings, {CIO::iCAN}) // Левый поворотник + SETTING (iRightTurnLight, NotFixed, TInputSettings, {CIO::iCAN}) // Правый поворотник + SETTING (iTaho, NotFixed, TInputSettings, {CIO::iCAN}) // Тахометр +// SETTING (iEmergency, NotFixed, TInputSettings, {CIO::iCAN}) // Используется как статус + SETTING (Kxx, NotFixed, uint16_t, 37) // Калибровочный коэф. холостого хода + +//************************** ВЫХОДЫ ************************************************************// + + SETTING (oLights, NotFixed, uint32_t, oBIT(oCAN)) +// SETTING (oAutoStart, NotFixed, uint32_t, oBIT(oCAN)) // События автозапуска +// SETTING (oEmergency, NotFixed, uint32_t, oBIT(oBrownViolet)) // Выход на триггерную кнопку. + SETTING (oKLine1Relay, NotFixed, uint32_t, 0) + SETTING (oKLine2Relay, NotFixed, uint32_t, 0) + + SETTING (oLockDoors, NotFixed, uint32_t, oBIT(oCAN)) // Запереть все двери + SETTING (oUnlockDoors, NotFixed, uint32_t, oBIT(oCAN)) // Отпереть все двери + SETTING (oImmBypass, NotFixed, uint32_t, oBIT(oBrownWhite)) + SETTING (oBrake, NotFixed, uint32_t, oBIT(oBrownYellow)) + + SETTING (oIgn, NotFixed, uint32_t, 0) // Включение зажигания + SETTING (oAuxIgn, NotFixed, uint32_t, 0) // Дополнительная линия зажигания + SETTING (oAcc, NotFixed, uint32_t, 0) // Аксессуары + SETTING (oCrank, NotFixed, uint32_t, 0) // Стартер + + + +//--------- Check boxs -----------------------------------------------------------------// + SETTING (SSB, NotFixed, bit_t, 1) + SETTING (DriveBuiltinSystem, NotFixed, bit_t, 1) // управлять штатной системой автомобиля + SETTING (SlaveModeEnable, NotFixed, bit_t, 1) // включить слейв + SETTING (SlaveDisarmWithTagOnly,NotFixed, bit_t, 1) // снятие с охраны по SLAVE-входу только при наличии телефона-метки, прерывание тревоги не запрещает + SETTING (SetReadyMode, NotFixed, uint8_t, 2) // режим включения поддержки зажигания + SETTING (ClrReadyMode, NotFixed, uint8_t, 1) + SETTING (LightsArm, NotFixed, bit_t, 0) // при включении охраны + SETTING (LightsDisarm, NotFixed, bit_t, 0) // при выключении охраны + +//--------- Последовательности -------------------- + SETTING (seqProg6, NotFixed, TSequence, {qMS(100),6}) + SETTING (seqProg8, Fixed, TSequence, {qMS(10),25}) // аварийка: импульс 250 мс + SETTING (seqProg9, Fixed, TSequence, {qMS(10),15}) // аварийка: импульс 150 мс + +//--------- Переименование входов/выходов --------- +// SETTING_NAME (iEmergency, "<Аварийная сигнализация>") +// SETTING_NAME (oEmergency, "<Управление поворотниками через кнопку>") +// SETTING_NAME (oWireLock, "<Запирание дверей при IgnOn>") +// SETTING_NAME (oWireUnlock, "<Отпирание дверей при IgnOn>") + +//************************** Настройки CAN-прошивки ***********************************************// + + SETTING_CAN (SET1, NotFixed, bit_t, 0, "Настройка 1") + SETTING_CAN (SET2, NotFixed, uint8_t, 0, "Настройка 2|Вкл|Выкл") + SETTING_CAN (SET3, NotFixed, uint8_t, 1, "Настройка 3|Вкл|Выкл|He знаю") + +#undef SETTING +#undef SETTING_RSRV +#undef SETTING_ALIAS +#undef SETTING_CAN + +//************************** The End **************************************************************// + + + diff --git a/src/immo/Immo.h b/src/immo/Immo.h new file mode 100644 index 0000000..214708b --- /dev/null +++ b/src/immo/Immo.h @@ -0,0 +1,16 @@ +#ifndef __IMMO_H_ +#define __IMMO_H_ +#include +#include +#include + +void CalcUDS(uint8_t *sec_ask, uint8_t *sec_ans );//функция для расчёта security access +void GetImmoOut(uint8_t *req, uint8_t *ans, uint8_t *key ); +void shortGetImmoOut(uint8_t *state, uint8_t *key); +bool CheckArray(uint8_t *a,uint8_t *b, uint8_t len); +bool CheckKey(uint8_t *req, uint8_t *ans, uint8_t *key ); + + +#endif /* __IMMO_H_ */ + + diff --git a/src/immo/immo.cpp b/src/immo/immo.cpp new file mode 100644 index 0000000..fb31eb2 --- /dev/null +++ b/src/immo/immo.cpp @@ -0,0 +1,30 @@ +#include "Immo.h" +void CalcUDS(uint8_t *sec_ask, uint8_t *sec_ans )//функция для расчёта security access +{ + +} +void GetImmoOut(uint8_t *req, uint8_t *ans, uint8_t *key ) +{//функция для расчёта ответа иммо + +} +void shortGetImmoOut(uint8_t *state, uint8_t *key) +{//функция для расчёта ответа иммо + +} +bool CheckArray(uint8_t *a,uint8_t *b, uint8_t len) +{ + uint8_t count=0; + for(int i=0;i=len-1) + return 1; + return 0; +} +bool CheckKey(uint8_t *req, uint8_t *ans, uint8_t *key ) +{ //функция для проверуи валидности ключа при обучении + unsigned char state[16] = { 0 }; + return CheckArray(state, ans, 8); +} \ No newline at end of file diff --git a/src/immo/immo.md b/src/immo/immo.md new file mode 100644 index 0000000..b7482b9 --- /dev/null +++ b/src/immo/immo.md @@ -0,0 +1 @@ +# Обход штатного иммобилайзера \ No newline at end of file diff --git a/src/source/SourcePath.h b/src/source/SourcePath.h new file mode 100644 index 0000000..ad75096 --- /dev/null +++ b/src/source/SourcePath.h @@ -0,0 +1,11 @@ + +#ifndef SOURCEPATH_H_ +#define SOURCEPATH_H_ +// здесь указываются пути к конкретной прошивке, которую необходимо собрать + +#define SRC_HEADER "CAN_FW.h" +#define SRC_SETTINGS "SettingsCANTable.h" +#define SRC_FILE1 "CAN_Inputs.h" +#define SRC_FILE2 "CAN_Outputs.h" + +#endif /* SOURCEPATH_H_ */ diff --git a/sys/M1_CAN_FW.ld b/sys/M1_CAN_FW.ld new file mode 100644 index 0000000..3c8872a --- /dev/null +++ b/sys/M1_CAN_FW.ld @@ -0,0 +1,147 @@ +/************************************************* +* linker script for STM32F10xCL +************************************************/ + +ENTRY (CanFuctTable) + + +MEMORY +{ + /* оперативку не используем! */ + /* RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0 */ + + /* используем флеш 112K .. 128K */ + FLASH (rx) : ORIGIN = (0x08000000 + 112K), LENGTH = 16K +} + +/* higher address of the user mode stack */ +PROVIDE ( _estack = ALIGN(ORIGIN(RAM) + LENGTH(RAM) - 8 ,8) ); + +SECTIONS +{ + + .entrance_vector : + { + _stext = .; + + . = ALIGN(4); + KEEP(*(.entrance_vector)) + . = ALIGN(4); + } > FLASH =0xFFFFFFFF + + .text : + { + __ctors_start__ = .; + KEEP(SORT(*)(.init_array)) /* eabi uses .init_array for static constructor lists */ + __ctors_end__ = .; + + __dtors_start__ = .; + __dtors_end__ = .; + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + + *(.eh_frame_hdr) + *(.eh_frame) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + } > FLASH =0xFFFFFFFF + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH =0xFFFFFFFF + __exidx_end = .; + + .text.align : + { + . = ALIGN(8); + _etext = .; + _sidata = _etext; /* start of initialized data label */ + } > FLASH =0xFFFFFFFF + + /* конец данных во флеш - кладём сюда таблицу с настройками и контрольную сумму */ + .text.SettingsCanName : + { + . = ALIGN(4); + KEEP(*(.SettingsCanName)) + } > FLASH + .text.SettingsVarName : + { + . = ALIGN(4); + KEEP(*(.SettingsVarName)) + } > FLASH + .text.SettingsTable : + { + . = ALIGN(4); + KEEP(*(.SettingsTable)) + } > FLASH + .text.CheckSum : + { + . = ALIGN(4); + KEEP(*(.CheckSum)) + } > FLASH + + +/************************************************************** +* Remove the debugging information from the standard libraries +***************************************************************/ + +/* remove the debugging information from the standard libraries */ +DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +/* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +/* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + +/* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } +/* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } +/* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } +/* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } +/* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + +} diff --git a/sys/M3_CAN_FW.ld b/sys/M3_CAN_FW.ld new file mode 100644 index 0000000..70a9225 --- /dev/null +++ b/sys/M3_CAN_FW.ld @@ -0,0 +1,147 @@ +/************************************************* +* linker script for STM32F4xx +************************************************/ + +ENTRY (CanFuctTable) + + +MEMORY +{ + /* оперативку не используем! */ + /* RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 0 */ + + /* используем флеш 48K .. 64K */ + FLASH (rx) : ORIGIN = (0x08000000 + 48K), LENGTH = 16K +} + +/* higher address of the user mode stack */ +PROVIDE ( _estack = ALIGN(ORIGIN(RAM) + LENGTH(RAM) - 8 ,8) ); + +SECTIONS +{ + + .entrance_vector : + { + _stext = .; + + . = ALIGN(4); + KEEP(*(.entrance_vector)) + . = ALIGN(4); + } > FLASH =0xFFFFFFFF + + .text : + { + __ctors_start__ = .; + KEEP(SORT(*)(.init_array)) /* eabi uses .init_array for static constructor lists */ + __ctors_end__ = .; + + __dtors_start__ = .; + __dtors_end__ = .; + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + + *(.eh_frame_hdr) + *(.eh_frame) + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + *(.eh_frame_hdr) + *(.eh_frame) + + *(.glue_7) + *(.glue_7t) + . = ALIGN(4); + } > FLASH =0xFFFFFFFF + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH =0xFFFFFFFF + __exidx_end = .; + + .text.align : + { + . = ALIGN(8); + _etext = .; + _sidata = _etext; /* start of initialized data label */ + } > FLASH =0xFFFFFFFF + + /* конец данных во флеш - кладём сюда таблицу с настройками и контрольную сумму */ + .text.SettingsCanName : + { + . = ALIGN(4); + KEEP(*(.SettingsCanName)) + } > FLASH + .text.SettingsVarName : + { + . = ALIGN(4); + KEEP(*(.SettingsVarName)) + } > FLASH + .text.SettingsTable : + { + . = ALIGN(4); + KEEP(*(.SettingsTable)) + } > FLASH + .text.CheckSum : + { + . = ALIGN(4); + KEEP(*(.CheckSum)) + } > FLASH + + +/************************************************************** +* Remove the debugging information from the standard libraries +***************************************************************/ + +/* remove the debugging information from the standard libraries */ +DISCARD : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + +/* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } +/* + * DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + +/* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } +/* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } +/* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } +/* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } +/* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + +} diff --git a/sys/STM32F107.svd b/sys/STM32F107.svd new file mode 100644 index 0000000..c1fd178 --- /dev/null +++ b/sys/STM32F107.svd @@ -0,0 +1,42416 @@ + + + STM32F107 + 1.1 + STM32F107 + + CM3 + r1p1 + little + false + false + 4 + false + + + + 8 + + 32 + + 0x20 + 0x0 + 0xFFFFFFFF + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + + CR + CR + Power control register + (PWR_CR) + 0x0 + 0x20 + read-write + 0x00000000 + + + LPDS + Low Power Deep Sleep + 0 + 1 + + + PDDS + Power Down Deep Sleep + 1 + 1 + + + CWUF + Clear Wake-up Flag + 2 + 1 + + + CSBF + Clear STANDBY Flag + 3 + 1 + + + PVDE + Power Voltage Detector + Enable + 4 + 1 + + + PLS + PVD Level Selection + 5 + 3 + + + DBP + Disable Backup Domain write + protection + 8 + 1 + + + + + CSR + CSR + Power control register + (PWR_CR) + 0x4 + 0x20 + 0x00000000 + + + WUF + Wake-Up Flag + 0 + 1 + read-only + + + SBF + STANDBY Flag + 1 + 1 + read-only + + + PVDO + PVD Output + 2 + 1 + read-only + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global interrupt + 5 + + + + CR + CR + Clock control register + 0x0 + 0x20 + 0x00000083 + + + HSION + Internal High Speed clock + enable + 0 + 1 + read-write + + + HSIRDY + Internal High Speed clock ready + flag + 1 + 1 + read-only + + + HSITRIM + Internal High Speed clock + trimming + 3 + 5 + read-write + + + HSICAL + Internal High Speed clock + Calibration + 8 + 8 + read-only + + + HSEON + External High Speed clock + enable + 16 + 1 + read-write + + + HSERDY + External High Speed clock ready + flag + 17 + 1 + read-only + + + HSEBYP + External High Speed clock + Bypass + 18 + 1 + read-write + + + CSSON + Clock Security System + enable + 19 + 1 + read-write + + + PLLON + PLL enable + 24 + 1 + read-write + + + PLLRDY + PLL clock ready flag + 25 + 1 + read-only + + + PLL2ON + PLL2 enable + 26 + 1 + read-write + + + PLL2RDY + PLL2 clock ready flag + 27 + 1 + read-only + + + PLL3ON + PLL3 enable + 28 + 1 + read-write + + + PLL3RDY + PLL3 clock ready flag + 29 + 1 + read-only + + + + + CFGR + CFGR + Clock configuration register + (RCC_CFGR) + 0x4 + 0x20 + 0x00000000 + + + SW + System clock Switch + 0 + 2 + read-write + + + SWS + System Clock Switch Status + 2 + 2 + read-only + + + HPRE + AHB prescaler + 4 + 4 + read-write + + + PPRE1 + APB Low speed prescaler + (APB1) + 8 + 3 + read-write + + + PPRE2 + APB High speed prescaler + (APB2) + 11 + 3 + read-write + + + ADCPRE + ADC prescaler + 14 + 2 + read-write + + + PLLSRC + PLL entry clock source + 16 + 1 + read-write + + + PLLXTPRE + HSE divider for PLL entry + 17 + 1 + read-write + + + PLLMUL + PLL Multiplication Factor + 18 + 4 + read-write + + + OTGFSPRE + USB OTG FS prescaler + 22 + 1 + read-write + + + MCO + Microcontroller clock + output + 24 + 4 + read-write + + + + + CIR + CIR + Clock interrupt register + (RCC_CIR) + 0x8 + 0x20 + 0x00000000 + + + LSIRDYF + LSI Ready Interrupt flag + 0 + 1 + read-only + + + LSERDYF + LSE Ready Interrupt flag + 1 + 1 + read-only + + + HSIRDYF + HSI Ready Interrupt flag + 2 + 1 + read-only + + + HSERDYF + HSE Ready Interrupt flag + 3 + 1 + read-only + + + PLLRDYF + PLL Ready Interrupt flag + 4 + 1 + read-only + + + PLL2RDYF + PLL2 Ready Interrupt flag + 5 + 1 + read-only + + + PLL3RDYF + PLL3 Ready Interrupt flag + 6 + 1 + read-only + + + CSSF + Clock Security System Interrupt + flag + 7 + 1 + read-only + + + LSIRDYIE + LSI Ready Interrupt Enable + 8 + 1 + read-write + + + LSERDYIE + LSE Ready Interrupt Enable + 9 + 1 + read-write + + + HSIRDYIE + HSI Ready Interrupt Enable + 10 + 1 + read-write + + + HSERDYIE + HSE Ready Interrupt Enable + 11 + 1 + read-write + + + PLLRDYIE + PLL Ready Interrupt Enable + 12 + 1 + read-write + + + PLL2RDYIE + PLL2 Ready Interrupt + Enable + 13 + 1 + read-write + + + PLL3RDYIE + PLL3 Ready Interrupt + Enable + 14 + 1 + read-write + + + LSIRDYC + LSI Ready Interrupt Clear + 16 + 1 + write-only + + + LSERDYC + LSE Ready Interrupt Clear + 17 + 1 + write-only + + + HSIRDYC + HSI Ready Interrupt Clear + 18 + 1 + write-only + + + HSERDYC + HSE Ready Interrupt Clear + 19 + 1 + write-only + + + PLLRDYC + PLL Ready Interrupt Clear + 20 + 1 + write-only + + + PLL2RDYC + PLL2 Ready Interrupt Clear + 21 + 1 + write-only + + + PLL3RDYC + PLL3 Ready Interrupt Clear + 22 + 1 + write-only + + + CSSC + Clock security system interrupt + clear + 23 + 1 + write-only + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + (RCC_APB2RSTR) + 0xC + 0x20 + read-write + 0x000000000 + + + AFIORST + Alternate function I/O + reset + 0 + 1 + + + IOPARST + IO port A reset + 2 + 1 + + + IOPBRST + IO port B reset + 3 + 1 + + + IOPCRST + IO port C reset + 4 + 1 + + + IOPDRST + IO port D reset + 5 + 1 + + + IOPERST + IO port E reset + 6 + 1 + + + ADC1RST + ADC 1 interface reset + 9 + 1 + + + ADC2RST + ADC 2 interface reset + 10 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + (RCC_APB1RSTR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TIM2RST + Timer 2 reset + 0 + 1 + + + TIM3RST + Timer 3 reset + 1 + 1 + + + TIM4RST + Timer 4 reset + 2 + 1 + + + TIM5RST + Timer 5 reset + 3 + 1 + + + TIM6RST + Timer 6 reset + 4 + 1 + + + TIM7RST + Timer 7 reset + 5 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + SPI3RST + SPI3 reset + 15 + 1 + + + USART2RST + USART 2 reset + 17 + 1 + + + USART3RST + USART 3 reset + 18 + 1 + + + USART4RST + USART 4 reset + 19 + 1 + + + USART5RST + USART 5 reset + 20 + 1 + + + I2C1RST + I2C1 reset + 21 + 1 + + + I2C2RST + I2C2 reset + 22 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + BKPRST + Backup interface reset + 27 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC interface reset + 29 + 1 + + + + + AHBENR + AHBENR + AHB Peripheral Clock enable register + (RCC_AHBENR) + 0x14 + 0x20 + read-write + 0x00000014 + + + DMA1EN + DMA1 clock enable + 0 + 1 + + + DMA2EN + DMA2 clock enable + 1 + 1 + + + SRAMEN + SRAM interface clock + enable + 2 + 1 + + + FLITFEN + FLITF clock enable + 4 + 1 + + + CRCEN + CRC clock enable + 6 + 1 + + + OTGFSEN + USB OTG FS clock enable + 12 + 1 + + + ETHMACEN + Ethernet MAC clock enable + 14 + 1 + + + ETHMACTXEN + Ethernet MAC TX clock + enable + 15 + 1 + + + ETHMACRXEN + Ethernet MAC RX clock + enable + 16 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable register + (RCC_APB2ENR) + 0x18 + 0x20 + read-write + 0x00000000 + + + AFIOEN + Alternate function I/O clock + enable + 0 + 1 + + + IOPAEN + I/O port A clock enable + 2 + 1 + + + IOPBEN + I/O port B clock enable + 3 + 1 + + + IOPCEN + I/O port C clock enable + 4 + 1 + + + IOPDEN + I/O port D clock enable + 5 + 1 + + + IOPEEN + I/O port E clock enable + 6 + 1 + + + ADC1EN + ADC 1 interface clock + enable + 9 + 1 + + + ADC2EN + ADC 2 interface clock + enable + 10 + 1 + + + TIM1EN + TIM1 Timer clock enable + 11 + 1 + + + SPI1EN + SPI 1 clock enable + 12 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable register + (RCC_APB1ENR) + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM2EN + Timer 2 clock enable + 0 + 1 + + + TIM3EN + Timer 3 clock enable + 1 + 1 + + + TIM4EN + Timer 4 clock enable + 2 + 1 + + + TIM5EN + Timer 5 clock enable + 3 + 1 + + + TIM6EN + Timer 6 clock enable + 4 + 1 + + + TIM7EN + Timer 7 clock enable + 5 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + SPI2EN + SPI 2 clock enable + 14 + 1 + + + SPI3EN + SPI 3 clock enable + 15 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + USART3EN + USART 3 clock enable + 18 + 1 + + + UART4EN + UART 4 clock enable + 19 + 1 + + + UART5EN + UART 5 clock enable + 20 + 1 + + + I2C1EN + I2C 1 clock enable + 21 + 1 + + + I2C2EN + I2C 2 clock enable + 22 + 1 + + + CAN1EN + CAN1 clock enable + 25 + 1 + + + CAN2EN + CAN2 clock enable + 26 + 1 + + + BKPEN + Backup interface clock + enable + 27 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + + + BDCR + BDCR + Backup domain control register + (RCC_BDCR) + 0x20 + 0x20 + 0x00000000 + + + LSEON + External Low Speed oscillator + enable + 0 + 1 + read-write + + + LSERDY + External Low Speed oscillator + ready + 1 + 1 + read-only + + + LSEBYP + External Low Speed oscillator + bypass + 2 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + + + CSR + CSR + Control/status register + (RCC_CSR) + 0x24 + 0x20 + 0x0C000000 + + + LSION + Internal low speed oscillator + enable + 0 + 1 + read-write + + + LSIRDY + Internal low speed oscillator + ready + 1 + 1 + read-only + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + PINRSTF + PIN reset flag + 26 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + IWDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + + + AHBRSTR + AHBRSTR + AHB peripheral clock reset register + (RCC_AHBRSTR) + 0x28 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS reset + 12 + 1 + + + ETHMACRST + Ethernet MAC reset + 14 + 1 + + + + + CFGR2 + CFGR2 + Clock configuration register2 + (RCC_CFGR2) + 0x2C + 0x20 + read-write + 0x00000000 + + + PREDIV1 + PREDIV1 division factor + 0 + 4 + + + PREDIV2 + PREDIV2 division factor + 4 + 4 + + + PLL2MUL + PLL2 Multiplication Factor + 8 + 4 + + + PLL3MUL + PLL3 Multiplication Factor + 12 + 4 + + + PREDIV1SRC + PREDIV1 entry clock source + 16 + 1 + + + I2S2SRC + I2S2 clock source + 17 + 1 + + + I2S3SRC + I2S3 clock source + 18 + 1 + + + + + + + GPIOA + General purpose I/O + GPIO + 0x40010800 + + 0x0 + 0x400 + registers + + + + CRL + CRL + Port configuration register low + (GPIOn_CRL) + 0x0 + 0x20 + read-write + 0x44444444 + + + MODE0 + Port n.0 mode bits + 0 + 2 + + + CNF0 + Port n.0 configuration + bits + 2 + 2 + + + MODE1 + Port n.1 mode bits + 4 + 2 + + + CNF1 + Port n.1 configuration + bits + 6 + 2 + + + MODE2 + Port n.2 mode bits + 8 + 2 + + + CNF2 + Port n.2 configuration + bits + 10 + 2 + + + MODE3 + Port n.3 mode bits + 12 + 2 + + + CNF3 + Port n.3 configuration + bits + 14 + 2 + + + MODE4 + Port n.4 mode bits + 16 + 2 + + + CNF4 + Port n.4 configuration + bits + 18 + 2 + + + MODE5 + Port n.5 mode bits + 20 + 2 + + + CNF5 + Port n.5 configuration + bits + 22 + 2 + + + MODE6 + Port n.6 mode bits + 24 + 2 + + + CNF6 + Port n.6 configuration + bits + 26 + 2 + + + MODE7 + Port n.7 mode bits + 28 + 2 + + + CNF7 + Port n.7 configuration + bits + 30 + 2 + + + + + CRH + CRH + Port configuration register high + (GPIOn_CRL) + 0x4 + 0x20 + read-write + 0x44444444 + + + MODE8 + Port n.8 mode bits + 0 + 2 + + + CNF8 + Port n.8 configuration + bits + 2 + 2 + + + MODE9 + Port n.9 mode bits + 4 + 2 + + + CNF9 + Port n.9 configuration + bits + 6 + 2 + + + MODE10 + Port n.10 mode bits + 8 + 2 + + + CNF10 + Port n.10 configuration + bits + 10 + 2 + + + MODE11 + Port n.11 mode bits + 12 + 2 + + + CNF11 + Port n.11 configuration + bits + 14 + 2 + + + MODE12 + Port n.12 mode bits + 16 + 2 + + + CNF12 + Port n.12 configuration + bits + 18 + 2 + + + MODE13 + Port n.13 mode bits + 20 + 2 + + + CNF13 + Port n.13 configuration + bits + 22 + 2 + + + MODE14 + Port n.14 mode bits + 24 + 2 + + + CNF14 + Port n.14 configuration + bits + 26 + 2 + + + MODE15 + Port n.15 mode bits + 28 + 2 + + + CNF15 + Port n.15 configuration + bits + 30 + 2 + + + + + IDR + IDR + Port input data register + (GPIOn_IDR) + 0x8 + 0x20 + read-only + 0x00000000 + + + IDR0 + Port input data + 0 + 1 + + + IDR1 + Port input data + 1 + 1 + + + IDR2 + Port input data + 2 + 1 + + + IDR3 + Port input data + 3 + 1 + + + IDR4 + Port input data + 4 + 1 + + + IDR5 + Port input data + 5 + 1 + + + IDR6 + Port input data + 6 + 1 + + + IDR7 + Port input data + 7 + 1 + + + IDR8 + Port input data + 8 + 1 + + + IDR9 + Port input data + 9 + 1 + + + IDR10 + Port input data + 10 + 1 + + + IDR11 + Port input data + 11 + 1 + + + IDR12 + Port input data + 12 + 1 + + + IDR13 + Port input data + 13 + 1 + + + IDR14 + Port input data + 14 + 1 + + + IDR15 + Port input data + 15 + 1 + + + + + ODR + ODR + Port output data register + (GPIOn_ODR) + 0xC + 0x20 + read-write + 0x00000000 + + + ODR0 + Port output data + 0 + 1 + + + ODR1 + Port output data + 1 + 1 + + + ODR2 + Port output data + 2 + 1 + + + ODR3 + Port output data + 3 + 1 + + + ODR4 + Port output data + 4 + 1 + + + ODR5 + Port output data + 5 + 1 + + + ODR6 + Port output data + 6 + 1 + + + ODR7 + Port output data + 7 + 1 + + + ODR8 + Port output data + 8 + 1 + + + ODR9 + Port output data + 9 + 1 + + + ODR10 + Port output data + 10 + 1 + + + ODR11 + Port output data + 11 + 1 + + + ODR12 + Port output data + 12 + 1 + + + ODR13 + Port output data + 13 + 1 + + + ODR14 + Port output data + 14 + 1 + + + ODR15 + Port output data + 15 + 1 + + + + + BSRR + BSRR + Port bit set/reset register + (GPIOn_BSRR) + 0x10 + 0x20 + write-only + 0x00000000 + + + BS0 + Set bit 0 + 0 + 1 + + + BS1 + Set bit 1 + 1 + 1 + + + BS2 + Set bit 1 + 2 + 1 + + + BS3 + Set bit 3 + 3 + 1 + + + BS4 + Set bit 4 + 4 + 1 + + + BS5 + Set bit 5 + 5 + 1 + + + BS6 + Set bit 6 + 6 + 1 + + + BS7 + Set bit 7 + 7 + 1 + + + BS8 + Set bit 8 + 8 + 1 + + + BS9 + Set bit 9 + 9 + 1 + + + BS10 + Set bit 10 + 10 + 1 + + + BS11 + Set bit 11 + 11 + 1 + + + BS12 + Set bit 12 + 12 + 1 + + + BS13 + Set bit 13 + 13 + 1 + + + BS14 + Set bit 14 + 14 + 1 + + + BS15 + Set bit 15 + 15 + 1 + + + BR0 + Reset bit 0 + 16 + 1 + + + BR1 + Reset bit 1 + 17 + 1 + + + BR2 + Reset bit 2 + 18 + 1 + + + BR3 + Reset bit 3 + 19 + 1 + + + BR4 + Reset bit 4 + 20 + 1 + + + BR5 + Reset bit 5 + 21 + 1 + + + BR6 + Reset bit 6 + 22 + 1 + + + BR7 + Reset bit 7 + 23 + 1 + + + BR8 + Reset bit 8 + 24 + 1 + + + BR9 + Reset bit 9 + 25 + 1 + + + BR10 + Reset bit 10 + 26 + 1 + + + BR11 + Reset bit 11 + 27 + 1 + + + BR12 + Reset bit 12 + 28 + 1 + + + BR13 + Reset bit 13 + 29 + 1 + + + BR14 + Reset bit 14 + 30 + 1 + + + BR15 + Reset bit 15 + 31 + 1 + + + + + BRR + BRR + Port bit reset register + (GPIOn_BRR) + 0x14 + 0x20 + write-only + 0x00000000 + + + BR0 + Reset bit 0 + 0 + 1 + + + BR1 + Reset bit 1 + 1 + 1 + + + BR2 + Reset bit 1 + 2 + 1 + + + BR3 + Reset bit 3 + 3 + 1 + + + BR4 + Reset bit 4 + 4 + 1 + + + BR5 + Reset bit 5 + 5 + 1 + + + BR6 + Reset bit 6 + 6 + 1 + + + BR7 + Reset bit 7 + 7 + 1 + + + BR8 + Reset bit 8 + 8 + 1 + + + BR9 + Reset bit 9 + 9 + 1 + + + BR10 + Reset bit 10 + 10 + 1 + + + BR11 + Reset bit 11 + 11 + 1 + + + BR12 + Reset bit 12 + 12 + 1 + + + BR13 + Reset bit 13 + 13 + 1 + + + BR14 + Reset bit 14 + 14 + 1 + + + BR15 + Reset bit 15 + 15 + 1 + + + + + LCKR + LCKR + Port configuration lock + register + 0x18 + 0x20 + read-write + 0x00000000 + + + LCK0 + Port A Lock bit 0 + 0 + 1 + + + LCK1 + Port A Lock bit 1 + 1 + 1 + + + LCK2 + Port A Lock bit 2 + 2 + 1 + + + LCK3 + Port A Lock bit 3 + 3 + 1 + + + LCK4 + Port A Lock bit 4 + 4 + 1 + + + LCK5 + Port A Lock bit 5 + 5 + 1 + + + LCK6 + Port A Lock bit 6 + 6 + 1 + + + LCK7 + Port A Lock bit 7 + 7 + 1 + + + LCK8 + Port A Lock bit 8 + 8 + 1 + + + LCK9 + Port A Lock bit 9 + 9 + 1 + + + LCK10 + Port A Lock bit 10 + 10 + 1 + + + LCK11 + Port A Lock bit 11 + 11 + 1 + + + LCK12 + Port A Lock bit 12 + 12 + 1 + + + LCK13 + Port A Lock bit 13 + 13 + 1 + + + LCK14 + Port A Lock bit 14 + 14 + 1 + + + LCK15 + Port A Lock bit 15 + 15 + 1 + + + LCKK + Lock key + 16 + 1 + + + + + + + GPIOB + 0x40010C00 + + + GPIOC + 0x40011000 + + + GPIOD + 0x40011400 + + + GPIOE + 0x40011800 + + + GPIOF + 0x40011C00 + + + GPIOG + 0x40012000 + + + AFIO + Alternate function I/O + AFIO + 0x40010000 + + 0x0 + 0x400 + registers + + + + EVCR + EVCR + Event Control Register + (AFIO_EVCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + PIN + Pin selection + 0 + 4 + + + PORT + Port selection + 4 + 3 + + + EVOE + Event Output Enable + 7 + 1 + + + + + MAPR + MAPR + AF remap and debug I/O configuration + register (AFIO_MAPR) + 0x4 + 0x20 + 0x00000000 + + + SPI1_REMAP + SPI1 remapping + 0 + 1 + read-write + + + I2C1_REMAP + I2C1 remapping + 1 + 1 + read-write + + + USART1_REMAP + USART1 remapping + 2 + 1 + read-write + + + USART2_REMAP + USART2 remapping + 3 + 1 + read-write + + + USART3_REMAP + USART3 remapping + 4 + 2 + read-write + + + TIM1_REMAP + TIM1 remapping + 6 + 2 + read-write + + + TIM2_REMAP + TIM2 remapping + 8 + 2 + read-write + + + TIM3_REMAP + TIM3 remapping + 10 + 2 + read-write + + + TIM4_REMAP + TIM4 remapping + 12 + 1 + read-write + + + CAN1_REMAP + CAN1 remapping + 13 + 2 + read-write + + + PD01_REMAP + Port D0/Port D1 mapping on + OSCIN/OSCOUT + 15 + 1 + read-write + + + TIM5CH4_IREMAP + Set and cleared by + software + 16 + 1 + read-write + + + ETH_REMAP + Ethernet MAC I/O remapping + 21 + 1 + read-write + + + CAN2_REMAP + CAN2 I/O remapping + 22 + 1 + read-write + + + MII_RMII_SEL + MII or RMII selection + 23 + 1 + read-write + + + SWJ_CFG + Serial wire JTAG + configuration + 24 + 3 + write-only + + + SPI3_REMAP + SPI3/I2S3 remapping + 28 + 1 + read-write + + + TIM2ITR1_IREMAP + TIM2 internal trigger 1 + remapping + 29 + 1 + read-write + + + PTP_PPS_REMAP + Ethernet PTP PPS remapping + 30 + 1 + read-write + + + + + EXTICR1 + EXTICR1 + External interrupt configuration register 1 + (AFIO_EXTICR1) + 0x8 + 0x20 + read-write + 0x00000000 + + + EXTI0 + EXTI0 configuration + 0 + 4 + + + EXTI1 + EXTI1 configuration + 4 + 4 + + + EXTI2 + EXTI2 configuration + 8 + 4 + + + EXTI3 + EXTI3 configuration + 12 + 4 + + + + + EXTICR2 + EXTICR2 + External interrupt configuration register 2 + (AFIO_EXTICR2) + 0xC + 0x20 + read-write + 0x00000000 + + + EXTI4 + EXTI4 configuration + 0 + 4 + + + EXTI5 + EXTI5 configuration + 4 + 4 + + + EXTI6 + EXTI6 configuration + 8 + 4 + + + EXTI7 + EXTI7 configuration + 12 + 4 + + + + + EXTICR3 + EXTICR3 + External interrupt configuration register 3 + (AFIO_EXTICR3) + 0x10 + 0x20 + read-write + 0x00000000 + + + EXTI8 + EXTI8 configuration + 0 + 4 + + + EXTI9 + EXTI9 configuration + 4 + 4 + + + EXTI10 + EXTI10 configuration + 8 + 4 + + + EXTI11 + EXTI11 configuration + 12 + 4 + + + + + EXTICR4 + EXTICR4 + External interrupt configuration register 4 + (AFIO_EXTICR4) + 0x14 + 0x20 + read-write + 0x00000000 + + + EXTI12 + EXTI12 configuration + 0 + 4 + + + EXTI13 + EXTI13 configuration + 4 + 4 + + + EXTI14 + EXTI14 configuration + 8 + 4 + + + EXTI15 + EXTI15 configuration + 12 + 4 + + + + + MAPR2 + MAPR2 + AF remap and debug I/O configuration + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIM9_REMAP + TIM9 remapping + 5 + 1 + + + TIM10_REMAP + TIM10 remapping + 6 + 1 + + + TIM11_REMAP + TIM11 remapping + 7 + 1 + + + TIM13_REMAP + TIM13 remapping + 8 + 1 + + + TIM14_REMAP + TIM14 remapping + 9 + 1 + + + FSMC_NADV + NADV connect/disconnect + 10 + 1 + + + + + + + EXTI + EXTI + EXTI + 0x40010400 + + 0x0 + 0x400 + registers + + + TAMPER + Tamper interrupt + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 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0x20 + read-write + 0x00000000 + + + D10 + Backup data + 0 + 16 + + + + + DR11 + DR11 + Backup data register (BKP_DR) + 0x3C + 0x20 + read-write + 0x00000000 + + + DR11 + Backup data + 0 + 16 + + + + + DR12 + DR12 + Backup data register (BKP_DR) + 0x40 + 0x20 + read-write + 0x00000000 + + + DR12 + Backup data + 0 + 16 + + + + + DR13 + DR13 + Backup data register (BKP_DR) + 0x44 + 0x20 + read-write + 0x00000000 + + + DR13 + Backup data + 0 + 16 + + + + + DR14 + DR14 + Backup data register (BKP_DR) + 0x48 + 0x20 + read-write + 0x00000000 + + + D14 + Backup data + 0 + 16 + + + + + DR15 + DR15 + Backup data register (BKP_DR) + 0x4C + 0x20 + read-write + 0x00000000 + + + D15 + Backup data + 0 + 16 + + + + + DR16 + DR16 + Backup data register (BKP_DR) + 0x50 + 0x20 + read-write + 0x00000000 + + + D16 + Backup data + 0 + 16 + + + + + DR17 + DR17 + Backup data register (BKP_DR) + 0x54 + 0x20 + read-write + 0x00000000 + + + D17 + Backup data + 0 + 16 + + + + + DR18 + DR18 + Backup data register (BKP_DR) + 0x58 + 0x20 + read-write + 0x00000000 + + + D18 + Backup data + 0 + 16 + + + + + DR19 + DR19 + Backup data register (BKP_DR) + 0x5C + 0x20 + read-write + 0x00000000 + + + D19 + Backup data + 0 + 16 + + + + + DR20 + DR20 + Backup data register (BKP_DR) + 0x60 + 0x20 + read-write + 0x00000000 + + + D20 + Backup data + 0 + 16 + + + + + DR21 + DR21 + Backup data register (BKP_DR) + 0x64 + 0x20 + read-write + 0x00000000 + + + D21 + Backup data + 0 + 16 + + + + + DR22 + DR22 + Backup data register (BKP_DR) + 0x68 + 0x20 + read-write + 0x00000000 + + + D22 + Backup data + 0 + 16 + + + + + DR23 + DR23 + Backup data register (BKP_DR) + 0x6C + 0x20 + read-write + 0x00000000 + + + D23 + Backup data + 0 + 16 + + + + + DR24 + DR24 + Backup data register (BKP_DR) + 0x70 + 0x20 + read-write + 0x00000000 + + + D24 + Backup data + 0 + 16 + + + + + DR25 + DR25 + Backup data register (BKP_DR) + 0x74 + 0x20 + read-write + 0x00000000 + + + D25 + Backup data + 0 + 16 + + + + + DR26 + DR26 + Backup data register (BKP_DR) + 0x78 + 0x20 + read-write + 0x00000000 + + + D26 + Backup data + 0 + 16 + + + + + DR27 + DR27 + Backup data register (BKP_DR) + 0x7C + 0x20 + read-write + 0x00000000 + + + D27 + Backup data + 0 + 16 + + + + + DR28 + DR28 + Backup data register (BKP_DR) + 0x80 + 0x20 + read-write + 0x00000000 + + + D28 + Backup data + 0 + 16 + + + + + DR29 + DR29 + Backup data register (BKP_DR) + 0x84 + 0x20 + read-write + 0x00000000 + + + D29 + Backup data + 0 + 16 + + + + + DR30 + DR30 + Backup data register (BKP_DR) + 0x88 + 0x20 + read-write + 0x00000000 + + + D30 + Backup data + 0 + 16 + + + + + DR31 + DR31 + Backup data register (BKP_DR) + 0x8C + 0x20 + read-write + 0x00000000 + + + D31 + Backup data + 0 + 16 + + + + + DR32 + DR32 + Backup data register (BKP_DR) + 0x90 + 0x20 + read-write + 0x00000000 + + + D32 + Backup data + 0 + 16 + + + + + DR33 + DR33 + Backup data register (BKP_DR) + 0x94 + 0x20 + read-write + 0x00000000 + + + D33 + Backup data + 0 + 16 + + + + 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Filter bits + 2 + 1 + + + FB3 + Filter bits + 3 + 1 + + + FB4 + Filter bits + 4 + 1 + + + FB5 + Filter bits + 5 + 1 + + + FB6 + Filter bits + 6 + 1 + + + FB7 + Filter bits + 7 + 1 + + + FB8 + Filter bits + 8 + 1 + + + FB9 + Filter bits + 9 + 1 + + + FB10 + Filter bits + 10 + 1 + + + FB11 + Filter bits + 11 + 1 + + + FB12 + Filter bits + 12 + 1 + + + FB13 + Filter bits + 13 + 1 + + + FB14 + Filter bits + 14 + 1 + + + FB15 + Filter bits + 15 + 1 + + + FB16 + Filter bits + 16 + 1 + + + FB17 + Filter bits + 17 + 1 + + + FB18 + Filter bits + 18 + 1 + + + FB19 + Filter bits + 19 + 1 + + + FB20 + Filter bits + 20 + 1 + + + FB21 + Filter bits + 21 + 1 + + + FB22 + Filter bits + 22 + 1 + + + FB23 + Filter bits + 23 + 1 + + + FB24 + Filter bits + 24 + 1 + + + FB25 + Filter bits + 25 + 1 + + + FB26 + Filter bits + 26 + 1 + + + FB27 + Filter bits + 27 + 1 + + + FB28 + Filter bits + 28 + 1 + + + FB29 + Filter bits + 29 + 1 + + + FB30 + Filter bits + 30 + 1 + + + FB31 + Filter bits + 31 + 1 + + + + + + + ETHERNET_MAC + Ethernet: media access control + ETHERNET + 0x40028000 + + 0x0 + 0x61 + registers + + + ETH + Ethernet global interrupt + 61 + + + ETH_WKUP + Ethernet Wakeup through EXTI line + interrupt + 62 + + + + MACCR + MACCR + Ethernet MAC configuration register + (ETH_MACCR) + 0x0 + 0x20 + read-write + 0x00008000 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + DC + Deferral check + 4 + 1 + + + BL + Back-off limit + 5 + 2 + + + APCS + Automatic pad/CRC + stripping + 7 + 1 + + + RD + Retry disable + 9 + 1 + + + IPCO + IPv4 checksum offload + 10 + 1 + + + DM + Duplex mode + 11 + 1 + + + LM + Loopback mode + 12 + 1 + + + ROD + Receive own disable + 13 + 1 + + + FES + Fast Ethernet speed + 14 + 1 + + + CSD + Carrier sense disable + 16 + 1 + + + IFG + Interframe gap + 17 + 3 + + + JD + Jabber disable + 22 + 1 + + + WD + Watchdog disable + 23 + 1 + + + + + MACFFR + MACFFR + Ethernet MAC frame filter register + (ETH_MACCFFR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PM + Promiscuous mode + 0 + 1 + + + HU + Hash unicast + 1 + 1 + + + HM + Hash multicast + 2 + 1 + + + DAIF + Destination address inverse + filtering + 3 + 1 + + + PAM + Pass all multicast + 4 + 1 + + + BFD + Broadcast frames disable + 5 + 1 + + + PCF + Pass control frames + 6 + 2 + + + SAIF + Source address inverse + filtering + 8 + 1 + + + SAF + Source address filter + 9 + 1 + + + HPF + Hash or perfect filter + 10 + 1 + + + RA + Receive all + 31 + 1 + + + + + MACHTHR + MACHTHR + Ethernet MAC hash table high + register + 0x8 + 0x20 + read-write + 0x00000000 + + + HTH + Hash table high + 0 + 32 + + + + + MACHTLR + MACHTLR + Ethernet MAC hash table low + register + 0xC + 0x20 + read-write + 0x00000000 + + + HTL + Hash table low + 0 + 32 + + + + + MACMIIAR + MACMIIAR + Ethernet MAC MII address register + (ETH_MACMIIAR) + 0x10 + 0x20 + read-write + 0x00000000 + + + MB + MII busy + 0 + 1 + + + MW + MII write + 1 + 1 + + + CR + Clock range + 2 + 3 + + + MR + MII register + 6 + 5 + + + PA + PHY address + 11 + 5 + + + + + MACMIIDR + MACMIIDR + Ethernet MAC MII data register + (ETH_MACMIIDR) + 0x14 + 0x20 + read-write + 0x00000000 + + + MD + MII data + 0 + 16 + + + + + MACFCR + MACFCR + Ethernet MAC flow control register + (ETH_MACFCR) + 0x18 + 0x20 + read-write + 0x00000000 + + + FCB_BPA + Flow control busy/back pressure + activate + 0 + 1 + + + TFCE + Transmit flow control + enable + 1 + 1 + + + RFCE + Receive flow control + enable + 2 + 1 + + + UPFD + Unicast pause frame detect + 3 + 1 + + + PLT + Pause low threshold + 4 + 2 + + + ZQPD + Zero-quanta pause disable + 7 + 1 + + + PT + Pass control frames + 16 + 16 + + + + + MACVLANTR + MACVLANTR + Ethernet MAC VLAN tag register + (ETH_MACVLANTR) + 0x1C + 0x20 + read-write + 0x00000000 + + + VLANTI + VLAN tag identifier (for receive + frames) + 0 + 16 + + + VLANTC + 12-bit VLAN tag comparison + 16 + 1 + + + + + MACRWUFFR + MACRWUFFR + Ethernet MAC remote wakeup frame filter + register (ETH_MACRWUFFR) + 0x28 + 0x20 + read-write + 0x00000000 + + + MACPMTCSR + MACPMTCSR + Ethernet MAC PMT control and status register + (ETH_MACPMTCSR) + 0x2C + 0x20 + read-write + 0x00000000 + + + PD + Power down + 0 + 1 + + + MPE + Magic Packet enable + 1 + 1 + + + WFE + Wakeup frame enable + 2 + 1 + + + MPR + Magic packet received + 5 + 1 + + + WFR + Wakeup frame received + 6 + 1 + + + GU + Global unicast + 9 + 1 + + + WFFRPR + Wakeup frame filter register pointer + reset + 31 + 1 + + + + + MACSR + MACSR + Ethernet MAC interrupt status register + (ETH_MACSR) + 0x38 + 0x20 + read-write + 0x00000000 + + + PMTS + PMT status + 3 + 1 + + + MMCS + MMC status + 4 + 1 + + + MMCRS + MMC receive status + 5 + 1 + + + MMCTS + MMC transmit status + 6 + 1 + + + TSTS + Time stamp trigger status + 9 + 1 + + + + + MACIMR + MACIMR + Ethernet MAC interrupt mask register + (ETH_MACIMR) + 0x3C + 0x20 + read-write + 0x00000000 + + + PMTIM + PMT interrupt mask + 3 + 1 + + + TSTIM + Time stamp trigger interrupt + mask + 9 + 1 + + + + + MACA0HR + MACA0HR + Ethernet MAC address 0 high register + (ETH_MACA0HR) + 0x40 + 0x20 + 0x0010FFFF + + + MACA0H + MAC address0 high + 0 + 16 + read-write + + + MO + Always 1 + 31 + 1 + read-only + + + + + MACA0LR + MACA0LR + Ethernet MAC address 0 low + register + 0x44 + 0x20 + read-write + 0xFFFFFFFF + + + MACA0L + MAC address0 low + 0 + 32 + + + + + MACA1HR + MACA1HR + Ethernet MAC address 1 high register + (ETH_MACA1HR) + 0x48 + 0x20 + read-write + 0x0000FFFF + + + MACA1H + MAC address1 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA1LR + MACA1LR + Ethernet MAC address1 low + register + 0x4C + 0x20 + read-write + 0xFFFFFFFF + + + MACA1L + MAC address1 low + 0 + 32 + + + + + MACA2HR + MACA2HR + Ethernet MAC address 2 high register + (ETH_MACA2HR) + 0x50 + 0x20 + read-write + 0x0050 + + + ETH_MACA2HR + Ethernet MAC address 2 high + register + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA2LR + MACA2LR + Ethernet MAC address 2 low + register + 0x54 + 0x20 + read-write + 0xFFFFFFFF + + + MACA2L + MAC address2 low + 0 + 31 + + + + + MACA3HR + MACA3HR + Ethernet MAC address 3 high register + (ETH_MACA3HR) + 0x58 + 0x20 + read-write + 0x0000FFFF + + + MACA3H + MAC address3 high + 0 + 16 + + + MBC + Mask byte control + 24 + 6 + + + SA + Source address + 30 + 1 + + + AE + Address enable + 31 + 1 + + + + + MACA3LR + MACA3LR + Ethernet MAC address 3 low + register + 0x5C + 0x20 + read-write + 0xFFFFFFFF + + + MBCA3L + MAC address3 low + 0 + 32 + + + + + + + ETHERNET_MMC + Ethernet: MAC management counters + ETHERNET + 0x40028100 + + 0x0 + 0x400 + registers + + + + MMCCR + MMCCR + Ethernet MMC control register + (ETH_MMCCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + CR + Counter reset + 0 + 1 + + + CSR + Counter stop rollover + 1 + 1 + + + ROR + Reset on read + 2 + 1 + + + MCF + MMC counter freeze + 31 + 1 + + + + + MMCRIR + MMCRIR + Ethernet MMC receive interrupt register + (ETH_MMCRIR) + 0x4 + 0x20 + read-write + 0x00000000 + + + RFCES + Received frames CRC error + status + 5 + 1 + + + RFAES + Received frames alignment error + status + 6 + 1 + + + RGUFS + Received Good Unicast Frames + Status + 17 + 1 + + + + + MMCTIR + MMCTIR + Ethernet MMC transmit interrupt register + (ETH_MMCTIR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TGFSCS + Transmitted good frames single collision + status + 14 + 1 + + + TGFMSCS + Transmitted good frames more single + collision status + 15 + 1 + + + TGFS + Transmitted good frames + status + 21 + 1 + + + + + MMCRIMR + MMCRIMR + Ethernet MMC receive interrupt mask register + (ETH_MMCRIMR) + 0xC + 0x20 + read-write + 0x00000000 + + + RFCEM + Received frame CRC error + mask + 5 + 1 + + + RFAEM + Received frames alignment error + mask + 6 + 1 + + + RGUFM + Received good unicast frames + mask + 17 + 1 + + + + + MMCTIMR + MMCTIMR + Ethernet MMC transmit interrupt mask + register (ETH_MMCTIMR) + 0x10 + 0x20 + read-write + 0x00000000 + + + TGFSCM + Transmitted good frames single collision + mask + 14 + 1 + + + TGFMSCM + Transmitted good frames more single + collision mask + 15 + 1 + + + TGFM + Transmitted good frames + mask + 21 + 1 + + + + + MMCTGFSCCR + MMCTGFSCCR + Ethernet MMC transmitted good frames after a + single collision counter + 0x4C + 0x20 + read-only + 0x00000000 + + + TGFSCC + Transmitted good frames after a single + collision counter + 0 + 32 + + + + + MMCTGFMSCCR + MMCTGFMSCCR + Ethernet MMC transmitted good frames after + more than a single collision + 0x50 + 0x20 + read-only + 0x00000000 + + + TGFMSCC + Transmitted good frames after more than + a single collision counter + 0 + 32 + + + + + MMCTGFCR + MMCTGFCR + Ethernet MMC transmitted good frames counter + register + 0x68 + 0x20 + read-only + 0x00000000 + + + TGFC + Transmitted good frames + counter + 0 + 32 + + + + + MMCRFCECR + MMCRFCECR + Ethernet MMC received frames with CRC error + counter register + 0x94 + 0x20 + read-only + 0x00000000 + + + RFCFC + Received frames with CRC error + counter + 0 + 32 + + + + + MMCRFAECR + MMCRFAECR + Ethernet MMC received frames with alignment + error counter register + 0x98 + 0x20 + read-only + 0x00000000 + + + RFAEC + Received frames with alignment error + counter + 0 + 32 + + + + + MMCRGUFCR + MMCRGUFCR + MMC received good unicast frames counter + register + 0xC4 + 0x20 + read-only + 0x00000000 + + + RGUFC + Received good unicast frames + counter + 0 + 32 + + + + + + + ETHERNET_PTP + Ethernet: Precision time protocol + ETHERNET + 0x40028700 + + 0x0 + 0x400 + registers + + + + PTPTSCR + PTPTSCR + Ethernet PTP time stamp control register + (ETH_PTPTSCR) + 0x0 + 0x20 + read-write + 0x00000000 + + + TSE + Time stamp enable + 0 + 1 + + + TSFCU + Time stamp fine or coarse + update + 1 + 1 + + + TSSTI + Time stamp system time + initialize + 2 + 1 + + + TSSTU + Time stamp system time + update + 3 + 1 + + + TSITE + Time stamp interrupt trigger + enable + 4 + 1 + + + TSARU + Time stamp addend register + update + 5 + 1 + + + + + PTPSSIR + PTPSSIR + Ethernet PTP subsecond increment + register + 0x4 + 0x20 + read-write + 0x00000000 + + + STSSI + System time subsecond + increment + 0 + 8 + + + + + PTPTSHR + PTPTSHR + Ethernet PTP time stamp high + register + 0x8 + 0x20 + read-only + 0x00000000 + + + STS + System time second + 0 + 32 + + + + + PTPTSLR + PTPTSLR + Ethernet PTP time stamp low register + (ETH_PTPTSLR) + 0xC + 0x20 + read-only + 0x00000000 + + + STSS + System time subseconds + 0 + 31 + + + STPNS + System time positive or negative + sign + 31 + 1 + + + + + PTPTSHUR + PTPTSHUR + Ethernet PTP time stamp high update + register + 0x10 + 0x20 + read-write + 0x00000000 + + + TSUS + Time stamp update second + 0 + 32 + + + + + PTPTSLUR + PTPTSLUR + Ethernet PTP time stamp low update register + (ETH_PTPTSLUR) + 0x14 + 0x20 + read-write + 0x00000000 + + + TSUSS + Time stamp update + subseconds + 0 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unavailable + status + 2 + 1 + read-write + + + TJTS + Transmit jabber timeout + status + 3 + 1 + read-write + + + ROS + Receive overflow status + 4 + 1 + read-write + + + TUS + Transmit underflow status + 5 + 1 + read-write + + + RS + Receive status + 6 + 1 + read-write + + + RBUS + Receive buffer unavailable + status + 7 + 1 + read-write + + + RPSS + Receive process stopped + status + 8 + 1 + read-write + + + PWTS + Receive watchdog timeout + status + 9 + 1 + read-write + + + ETS + Early transmit status + 10 + 1 + read-write + + + FBES + Fatal bus error status + 13 + 1 + read-write + + + ERS + Early receive status + 14 + 1 + read-write + + + AIS + Abnormal interrupt summary + 15 + 1 + read-write + + + NIS + Normal interrupt summary + 16 + 1 + read-write + + + RPS + Receive process state + 17 + 3 + read-only + + + TPS + Transmit process state + 20 + 3 + read-only + + + EBS + Error bits status + 23 + 3 + read-only + + + MMCS + MMC status + 27 + 1 + read-only + + + PMTS + PMT status + 28 + 1 + read-only + + + TSTS + Time stamp trigger status + 29 + 1 + read-only + + + + + DMAOMR + DMAOMR + Ethernet DMA operation mode + register + 0x18 + 0x20 + read-write + 0x00000000 + + + SR + SR + 1 + 1 + + + OSF + OSF + 2 + 1 + + + RTC + RTC + 3 + 2 + + + FUGF + FUGF + 6 + 1 + + + FEF + FEF + 7 + 1 + + + ST + ST + 13 + 1 + + + TTC + TTC + 14 + 3 + + + FTF + FTF + 20 + 1 + + + TSF + TSF + 21 + 1 + + + DFRF + DFRF + 24 + 1 + + + RSF + RSF + 25 + 1 + + + DTCEFD + DTCEFD + 26 + 1 + + + + + DMAIER + DMAIER + Ethernet DMA interrupt enable + register + 0x1C + 0x20 + read-write + 0x00000000 + + + TIE + Transmit interrupt enable + 0 + 1 + + + TPSIE + Transmit process stopped interrupt + enable + 1 + 1 + + + TBUIE + Transmit buffer unavailable interrupt + enable + 2 + 1 + + + TJTIE + Transmit jabber timeout interrupt + enable + 3 + 1 + + + ROIE + Overflow interrupt enable + 4 + 1 + + + TUIE + Underflow interrupt enable + 5 + 1 + + + RIE + Receive interrupt enable + 6 + 1 + + + RBUIE + Receive buffer unavailable interrupt + enable + 7 + 1 + + + RPSIE + Receive process stopped interrupt + enable + 8 + 1 + + + RWTIE + receive watchdog timeout interrupt + enable + 9 + 1 + + + ETIE + Early transmit interrupt + enable + 10 + 1 + + + FBEIE + Fatal bus error interrupt + enable + 13 + 1 + + + ERIE + Early receive interrupt + enable + 14 + 1 + + + AISE + Abnormal interrupt summary + enable + 15 + 1 + + + NISE + Normal interrupt summary + enable + 16 + 1 + + + + + DMAMFBOCR + DMAMFBOCR + Ethernet DMA missed frame and buffer + overflow counter register + 0x20 + 0x20 + read-only + 0x00000000 + + + MFC + Missed frames by the + controller + 0 + 16 + + + OMFC + Overflow bit for missed frame + counter + 16 + 1 + + + MFA + Missed frames by the + application + 17 + 11 + + + OFOC + Overflow bit for FIFO overflow + counter + 28 + 1 + + + + + DMACHTDR + DMACHTDR + Ethernet DMA current host transmit + descriptor register + 0x48 + 0x20 + read-only + 0x00000000 + + + HTDAP + Host transmit descriptor address + pointer + 0 + 32 + + + + + DMACHRDR + DMACHRDR + Ethernet DMA current host receive descriptor + register + 0x4C + 0x20 + read-only + 0x00000000 + + + HRDAP + Host receive descriptor address + pointer + 0 + 32 + + + + + DMACHTBAR + DMACHTBAR + Ethernet DMA current host transmit buffer + address register + 0x50 + 0x20 + read-only + 0x00000000 + + + HTBAP + Host transmit buffer address + pointer + 0 + 32 + + + + + DMACHRBAR + DMACHRBAR + Ethernet DMA current host receive buffer + address register + 0x54 + 0x20 + read-only + 0x00000000 + + + HRBAP + Host receive buffer address + pointer + 0 + 32 + + + + + + + USB_OTG_GLOBAL + USB on the go full speed + USB_OTG + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 7 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host + mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size + register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + USB_OTG_HOST + USB on the go full speed + USB_OTG + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics + register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics + register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics + register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics + register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics + register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics + register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics + register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register + (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register + (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register + (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register + (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register + (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register + (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register + (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register + (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register + (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register + (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register + (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register + (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register + (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + USB_OTG_DEVICE + USB on the go full speed + USB_OTG + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + DOEPCTL1 + DOEPCTL1 + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + device endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + device endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DTXFSTS0 + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTG_FS device IN endpoint transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTG_FS device IN endpoint transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + USB_OTG_PWRCLK + USB on the go full speed + USB_OTG + 0x50000E00 + + 0x0 + 0x400 + registers + + + + FS_PCGCCTL + FS_PCGCCTL + OTG_FS power and clock gating control + register (OTG_FS_PCGCCTL) + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + DAC + Digital to analog converter + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + + CR + CR + Control register (DAC_CR) + 0x0 + 0x20 + read-write + 0x00000000 + + + EN1 + DAC channel1 enable + 0 + 1 + + + BOFF1 + DAC channel1 output buffer + disable + 1 + 1 + + + TEN1 + DAC channel1 trigger + enable + 2 + 1 + + + TSEL1 + DAC channel1 trigger + selection + 3 + 3 + + + WAVE1 + DAC channel1 noise/triangle wave + generation enable + 6 + 2 + + + MAMP1 + DAC channel1 mask/amplitude + selector + 8 + 4 + + + DMAEN1 + DAC channel1 DMA enable + 12 + 1 + + + EN2 + DAC channel2 enable + 16 + 1 + + + BOFF2 + DAC channel2 output buffer + disable + 17 + 1 + + + TEN2 + DAC channel2 trigger + enable + 18 + 1 + + + TSEL2 + DAC channel2 trigger + selection + 19 + 3 + + + WAVE2 + DAC channel2 noise/triangle wave + generation enable + 22 + 2 + + + MAMP2 + DAC channel2 mask/amplitude + selector + 24 + 4 + + + DMAEN2 + DAC channel2 DMA enable + 28 + 1 + + + + + SWTRIGR + SWTRIGR + DAC software trigger register + (DAC_SWTRIGR) + 0x4 + 0x20 + write-only + 0x00000000 + + + SWTRIG1 + DAC channel1 software + trigger + 0 + 1 + + + SWTRIG2 + DAC channel2 software + trigger + 1 + 1 + + + + + DHR12R1 + DHR12R1 + DAC channel1 12-bit right-aligned data + holding register(DAC_DHR12R1) + 0x8 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L1 + DHR12L1 + DAC channel1 12-bit left aligned data + holding register (DAC_DHR12L1) + 0xC + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R1 + DHR8R1 + DAC channel1 8-bit right aligned data + holding register (DAC_DHR8R1) + 0x10 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + + + DHR12R2 + DHR12R2 + DAC channel2 12-bit right aligned data + holding register (DAC_DHR12R2) + 0x14 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 0 + 12 + + + + + DHR12L2 + DHR12L2 + DAC channel2 12-bit left aligned data + holding register (DAC_DHR12L2) + 0x18 + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 12-bit left-aligned + data + 4 + 12 + + + + + DHR8R2 + DHR8R2 + DAC channel2 8-bit right-aligned data + holding register (DAC_DHR8R2) + 0x1C + 0x20 + read-write + 0x00000000 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 0 + 8 + + + + + DHR12RD + DHR12RD + Dual DAC 12-bit right-aligned data holding + register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 + Reserved + 0x20 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit right-aligned + data + 0 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 16 + 12 + + + + + DHR12LD + DHR12LD + DUAL DAC 12-bit left aligned data holding + register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 + Reserved + 0x24 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 12-bit left-aligned + data + 4 + 12 + + + DACC2DHR + DAC channel2 12-bit right-aligned + data + 20 + 12 + + + + + DHR8RD + DHR8RD + DUAL DAC 8-bit right aligned data holding + register (DAC_DHR8RD), Bits 31:16 Reserved + 0x28 + 0x20 + read-write + 0x00000000 + + + DACC1DHR + DAC channel1 8-bit right-aligned + data + 0 + 8 + + + DACC2DHR + DAC channel2 8-bit right-aligned + data + 8 + 8 + + + + + DOR1 + DOR1 + DAC channel1 data output register + (DAC_DOR1) + 0x2C + 0x20 + read-only + 0x00000000 + + + DACC1DOR + DAC channel1 data output + 0 + 12 + + + + + DOR2 + DOR2 + DAC channel2 data output register + (DAC_DOR2) + 0x30 + 0x20 + read-only + 0x00000000 + + + DACC2DOR + DAC channel2 data output + 0 + 12 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + DBGMCU_IDCODE + 0x0 + 0x20 + read-only + 0x0 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + CR + CR + DBGMCU_CR + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + DBG_IWDG_STOP + DBG_IWDG_STOP + 8 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 9 + 1 + + + DBG_TIM1_STOP + DBG_TIM1_STOP + 10 + 1 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 11 + 1 + + + DBG_TIM3_STOP + DBG_TIM3_STOP + 12 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 13 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 14 + 1 + + + DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT + 15 + 1 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 16 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 18 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 19 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 20 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 21 + 1 + + + + + + + UART4 + Universal asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + UART4 SR + 0x0 + 0x20 + 0x0 + + + PE + Parity error + 0 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + TC + Transmission complete + 6 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + + + DR + DR + UART4 DR + 0x4 + 0x20 + read-write + 0x0 + + + DR + DR + 0 + 9 + + + + + BRR + BRR + UART4 BRR + 0x8 + 0x20 + read-write + 0x0 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + + + CR1 + CR1 + UART4 CR1 + 0xC + 0x20 + read-write + 0x0 + + + SBK + Send break + 0 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + RE + Receiver enable + 2 + 1 + + + TE + Transmitter enable + 3 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + PS + Parity selection + 9 + 1 + + + PCE + Parity control enable + 10 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + M + Word length + 12 + 1 + + + UE + USART enable + 13 + 1 + + + + + CR2 + CR2 + UART4 CR2 + 0x10 + 0x20 + read-write + 0x0 + + + ADD + Address of the USART node + 0 + 4 + + + LBDL + lin break detection length + 5 + 1 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + STOP + STOP bits + 12 + 2 + + + LINEN + LIN mode enable + 14 + 1 + + + + + CR3 + CR3 + UART4 CR3 + 0x14 + 0x20 + read-write + 0x0 + + + EIE + Error interrupt enable + 0 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + + + + + UART5 + Universal asynchronous receiver + transmitter + USART + 0x40005000 + + 0x0 + 0x400 + registers + + + UART5 + UART5 global interrupt + 53 + + + + SR + SR + UART5 SR + 0x0 + 0x20 + 0x0 + + + PE + PE + 0 + 1 + read-only + + + FE + FE + 1 + 1 + read-only + + + NE + NE + 2 + 1 + read-only + + + ORE + ORE + 3 + 1 + read-only + + + IDLE + IDLE + 4 + 1 + read-only + + + RXNE + RXNE + 5 + 1 + read-write + + + TC + TC + 6 + 1 + read-write + + + TXE + TXE + 7 + 1 + read-only + + + LBD + LBD + 8 + 1 + read-write + + + + + DR + DR + UART5 DR + 0x4 + 0x20 + read-write + 0x0 + + + DR + DR + 0 + 9 + + + + + BRR + BRR + UART5 BRR + 0x8 + 0x20 + read-write + 0x0 + + + DIV_Fraction + DIV_Fraction + 0 + 4 + + + DIV_Mantissa + DIV_Mantissa + 4 + 12 + + + + + CR1 + CR1 + UART5 CR1 + 0xC + 0x20 + read-write + 0x0 + + + SBK + SBK + 0 + 1 + + + RWU + RWU + 1 + 1 + + + RE + RE + 2 + 1 + + + TE + TE + 3 + 1 + + + IDLEIE + IDLEIE + 4 + 1 + + + RXNEIE + RXNEIE + 5 + 1 + + + TCIE + TCIE + 6 + 1 + + + TXEIE + TXEIE + 7 + 1 + + + PEIE + PEIE + 8 + 1 + + + PS + PS + 9 + 1 + + + PCE + PCE + 10 + 1 + + + WAKE + WAKE + 11 + 1 + + + M + M + 12 + 1 + + + UE + UE + 13 + 1 + + + + + CR2 + CR2 + UART5 CR2 + 0x10 + 0x20 + read-write + 0x0 + + + ADD + ADD + 0 + 4 + + + LBDL + LBDL + 5 + 1 + + + LBDIE + LBDIE + 6 + 1 + + + STOP + STOP + 12 + 2 + + + LINEN + LINEN + 14 + 1 + + + + + CR3 + CR3 + UART5 CR3 + 0x14 + 0x20 + read-write + 0x0 + + + EIE + Error interrupt enable + 0 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + FLASH + FLASH + FLASH + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + Flash global interrupt + 4 + + + + ACR + ACR + Flash access control register + 0x0 + 0x20 + 0x00000030 + + + LATENCY + Latency + 0 + 3 + read-write + + + HLFCYA + Flash half cycle access + enable + 3 + 1 + read-write + + + PRFTBE + Prefetch buffer enable + 4 + 1 + read-write + + + PRFTBS + Prefetch buffer status + 5 + 1 + read-only + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 5 + 1 + read-write + + + WRPRTERR + Write protection error + 4 + 1 + read-write + + + PGERR + Programming error + 2 + 1 + read-write + + + BSY + Busy + 0 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x00000080 + + + PG + Programming + 0 + 1 + + + PER + Page Erase + 1 + 1 + + + MER + Mass Erase + 2 + 1 + + + OPTPG + Option byte programming + 4 + 1 + + + OPTER + Option byte erase + 5 + 1 + + + STRT + Start + 6 + 1 + + + LOCK + Lock + 7 + 1 + + + OPTWRE + Option bytes write enable + 9 + 1 + + + ERRIE + Error interrupt enable + 10 + 1 + + + EOPIE + End of operation interrupt + enable + 12 + 1 + + + + + AR + AR + Flash address register + 0x14 + 0x20 + write-only + 0x00000000 + + + FAR + Flash Address + 0 + 32 + + + + + OBR + OBR + Option byte register + 0x1C + 0x20 + read-only + 0x03FFFFFC + + + OPTERR + Option byte error + 0 + 1 + + + RDPRT + Read protection + 1 + 1 + + + WDG_SW + WDG_SW + 2 + 1 + + + nRST_STOP + nRST_STOP + 3 + 1 + + + nRST_STDBY + nRST_STDBY + 4 + 1 + + + Data0 + Data0 + 10 + 8 + + + Data1 + Data1 + 18 + 8 + + + + + WRPR + WRPR + Write protection register + 0x20 + 0x20 + read-only + 0xFFFFFFFF + + + WRP + Write protect + 0 + 32 + + + + + + + FSMC + Flexible static memory controller + FSMC + 0xA0000000 + + 0x0 + 0x1000 + registers + + + FSMC + FSMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + Attribute memory x databus HiZ + time + 24 + 8 + + + ATTHOLDx + Attribute memory x hold + time + 16 + 8 + + + ATTWAITx + Attribute memory x wait + time + 8 + 8 + + + ATTSETx + Attribute memory x setup + time + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECC result + 0 + 32 + + + + + PCR3 + PCR3 + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR3 + SR3 + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR4 + PCR4 + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR4 + SR4 + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40018000 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + Card Status + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + Card Status + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + Card Status + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + Card Status + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + TIM11 + General purpose timer + TIM + 0x40015400 + + 0x0 + 0x400 + registers + + + TIM1_TRG_COM + TIM1 Trigger and Commutation + interrupts + 26 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + + + TIM10 + 0x40015000 + + + TIM9 + General purpose timer + TIM + 0x40014C00 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + + + TIM12 + 0x40001800 + + + ADC3 + Analog to digital converter + ADC + 0x40013C00 + + 0x0 + 0x400 + registers + + + ADC1_2 + ADC1 and ADC2 global interrupt + 18 + + + ADC3 + ADC3 global interrupt + 47 + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DUALMOD + Dual mode selection + 16 + 4 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + SWSTART + Start conversion of regular + channels + 22 + 1 + + + JSWSTART + Start conversion of injected + channels + 21 + 1 + + + EXTTRIG + External trigger conversion mode for + regular channels + 20 + 1 + + + EXTSEL + External event select for regular + group + 17 + 3 + + + JEXTTRIG + External trigger conversion mode for + injected channels + 15 + 1 + + + JEXTSEL + External event select for injected + group + 12 + 3 + + + ALIGN + Data alignment + 11 + 1 + + + DMA + Direct memory access mode + 8 + 1 + + + RSTCAL + Reset calibration + 3 + 1 + + + CAL + A/D calibration + 2 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + 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Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + + + TIM14 + 0x40002000 + + + NVIC + Nested Vectored Interrupt + Controller + NVIC + 0xE000E100 + + 0x0 + 0x33D + registers + + + + ISER0 + ISER0 + Interrupt Set-Enable Register + 0x0 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ISER1 + ISER1 + Interrupt Set-Enable Register + 0x4 + 0x20 + read-write + 0x00000000 + + + SETENA + SETENA + 0 + 32 + + + + + ICER0 + ICER0 + Interrupt Clear-Enable + Register + 0x80 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ICER1 + ICER1 + Interrupt Clear-Enable + Register + 0x84 + 0x20 + read-write + 0x00000000 + + + CLRENA + CLRENA + 0 + 32 + + + + + ISPR0 + ISPR0 + Interrupt Set-Pending Register + 0x100 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ISPR1 + ISPR1 + Interrupt Set-Pending Register + 0x104 + 0x20 + read-write + 0x00000000 + + + SETPEND + SETPEND + 0 + 32 + + + + + ICPR0 + ICPR0 + Interrupt Clear-Pending + Register + 0x180 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + ICPR1 + ICPR1 + Interrupt Clear-Pending + Register + 0x184 + 0x20 + read-write + 0x00000000 + + + CLRPEND + CLRPEND + 0 + 32 + + + + + IABR0 + IABR0 + Interrupt Active Bit Register + 0x200 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IABR1 + IABR1 + Interrupt Active Bit Register + 0x204 + 0x20 + read-only + 0x00000000 + + + ACTIVE + ACTIVE + 0 + 32 + + + + + IPR0 + IPR0 + Interrupt Priority Register + 0x300 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR1 + IPR1 + Interrupt Priority Register + 0x304 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR2 + IPR2 + Interrupt Priority Register + 0x308 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR3 + IPR3 + Interrupt Priority Register + 0x30C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR4 + IPR4 + Interrupt Priority Register + 0x310 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR5 + IPR5 + Interrupt Priority Register + 0x314 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR6 + IPR6 + Interrupt Priority Register + 0x318 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR7 + IPR7 + Interrupt Priority Register + 0x31C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR8 + IPR8 + Interrupt Priority Register + 0x320 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR9 + IPR9 + Interrupt Priority Register + 0x324 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR10 + IPR10 + Interrupt Priority Register + 0x328 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR11 + IPR11 + Interrupt Priority Register + 0x32C + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR12 + IPR12 + Interrupt Priority Register + 0x330 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR13 + IPR13 + Interrupt Priority Register + 0x334 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + IPR14 + IPR14 + Interrupt Priority Register + 0x338 + 0x20 + read-write + 0x00000000 + + + IPR_N0 + IPR_N0 + 0 + 8 + + + IPR_N1 + IPR_N1 + 8 + 8 + + + IPR_N2 + IPR_N2 + 16 + 8 + + + IPR_N3 + IPR_N3 + 24 + 8 + + + + + + + MPU + Memory protection unit + MPU + 0xE000ED90 + + 0x0 + 0x15 + registers + + + + MPU_TYPER + MPU_TYPER + MPU type register + 0x0 + 0x20 + read-only + 0X00000800 + + + SEPARATE + Separate flag + 0 + 1 + + + DREGION + Number of MPU data regions + 8 + 8 + + + IREGION + Number of MPU instruction + regions + 16 + 8 + + + + + MPU_CTRL + MPU_CTRL + MPU control register + 0x4 + 0x20 + read-only + 0X00000000 + + + ENABLE + Enables the MPU + 0 + 1 + + + HFNMIENA + Enables the operation of MPU during hard + fault + 1 + 1 + + + PRIVDEFENA + Enable priviliged software access to + default memory map + 2 + 1 + + + + + MPU_RNR + MPU_RNR + MPU region number register + 0x8 + 0x20 + read-write + 0X00000000 + + + REGION + MPU region + 0 + 8 + + + + + MPU_RBAR + MPU_RBAR + MPU region base address + register + 0xC + 0x20 + read-write + 0X00000000 + + + REGION + MPU region field + 0 + 4 + + + VALID + MPU region number valid + 4 + 1 + + + ADDR + Region base address field + 5 + 27 + + + + + MPU_RASR + MPU_RASR + MPU region attribute and size + register + 0x10 + 0x20 + read-write + 0X00000000 + + + ENABLE + Region enable bit. + 0 + 1 + + + SIZE + Size of the MPU protection + region + 1 + 5 + + + SRD + Subregion disable bits + 8 + 8 + + + B + memory attribute + 16 + 1 + + + C + memory attribute + 17 + 1 + + + S + Shareable memory attribute + 18 + 1 + + + TEX + memory attribute + 19 + 3 + + + AP + Access permission + 24 + 3 + + + XN + Instruction access disable + bit + 28 + 1 + + + + + + + SCB_ACTRL + System control block ACTLR + SCB + 0xE000E008 + + 0x0 + 0x5 + registers + + + + ACTRL + ACTRL + Auxiliary control register + 0x0 + 0x20 + read-write + 0x00000000 + + + DISFOLD + DISFOLD + 2 + 1 + + + FPEXCODIS + FPEXCODIS + 10 + 1 + + + DISRAMODE + DISRAMODE + 11 + 1 + + + DISITMATBFLUSH + DISITMATBFLUSH + 12 + 1 + + + + + + + NVIC_STIR + Nested vectored interrupt + controller + NVIC + 0xE000EF00 + + 0x0 + 0x5 + registers + + + + STIR + STIR + Software trigger interrupt + register + 0x0 + 0x20 + read-write + 0x00000000 + + + INTID + Software generated interrupt + ID + 0 + 9 + + + + + + + SCB + System control block + SCB + 0xE000ED00 + + 0x0 + 0x41 + registers + + + + CPUID + CPUID + CPUID base register + 0x0 + 0x20 + read-only + 0x410FC241 + + + Revision + Revision number + 0 + 4 + + + PartNo + Part number of the + processor + 4 + 12 + + + Constant + Reads as 0xF + 16 + 4 + + + Variant + Variant number + 20 + 4 + + + Implementer + Implementer code + 24 + 8 + + + + + ICSR + ICSR + Interrupt control and state + register + 0x4 + 0x20 + read-write + 0x00000000 + + + VECTACTIVE + Active vector + 0 + 9 + + + RETTOBASE + Return to base level + 11 + 1 + + + VECTPENDING + Pending vector + 12 + 7 + + + ISRPENDING + Interrupt pending flag + 22 + 1 + + + PENDSTCLR + SysTick exception clear-pending + bit + 25 + 1 + + + PENDSTSET + SysTick exception set-pending + bit + 26 + 1 + + + PENDSVCLR + PendSV clear-pending bit + 27 + 1 + + + PENDSVSET + PendSV set-pending bit + 28 + 1 + + + NMIPENDSET + NMI set-pending bit. + 31 + 1 + + + + + VTOR + VTOR + Vector table offset register + 0x8 + 0x20 + read-write + 0x00000000 + + + TBLOFF + Vector table base offset + field + 9 + 21 + + + + + AIRCR + AIRCR + Application interrupt and reset control + register + 0xC + 0x20 + read-write + 0x00000000 + + + VECTRESET + VECTRESET + 0 + 1 + + + VECTCLRACTIVE + VECTCLRACTIVE + 1 + 1 + + + SYSRESETREQ + SYSRESETREQ + 2 + 1 + + + PRIGROUP + PRIGROUP + 8 + 3 + + + ENDIANESS + ENDIANESS + 15 + 1 + + + VECTKEYSTAT + Register key + 16 + 16 + + + + + SCR + SCR + System control register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLEEPONEXIT + SLEEPONEXIT + 1 + 1 + + + SLEEPDEEP + SLEEPDEEP + 2 + 1 + + + SEVEONPEND + Send Event on Pending bit + 4 + 1 + + + + + CCR + CCR + Configuration and control + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NONBASETHRDENA + Configures how the processor enters + Thread mode + 0 + 1 + + + USERSETMPEND + USERSETMPEND + 1 + 1 + + + UNALIGN__TRP + UNALIGN_ TRP + 3 + 1 + + + DIV_0_TRP + DIV_0_TRP + 4 + 1 + + + BFHFNMIGN + BFHFNMIGN + 8 + 1 + + + STKALIGN + STKALIGN + 9 + 1 + + + + + SHPR1 + SHPR1 + System handler priority + registers + 0x18 + 0x20 + read-write + 0x00000000 + + + PRI_4 + Priority of system handler + 4 + 0 + 8 + + + PRI_5 + Priority of system handler + 5 + 8 + 8 + + + PRI_6 + Priority of system handler + 6 + 16 + 8 + + + + + SHPR2 + SHPR2 + System handler priority + registers + 0x1C + 0x20 + read-write + 0x00000000 + + + PRI_11 + Priority of system handler + 11 + 24 + 8 + + + + + SHPR3 + SHPR3 + System handler priority + registers + 0x20 + 0x20 + read-write + 0x00000000 + + + PRI_14 + Priority of system handler + 14 + 16 + 8 + + + PRI_15 + Priority of system handler + 15 + 24 + 8 + + + + + SHCRS + SHCRS + System handler control and state + register + 0x24 + 0x20 + read-write + 0x00000000 + + + MEMFAULTACT + Memory management fault exception active + bit + 0 + 1 + + + BUSFAULTACT + Bus fault exception active + bit + 1 + 1 + + + USGFAULTACT + Usage fault exception active + bit + 3 + 1 + + + SVCALLACT + SVC call active bit + 7 + 1 + + + MONITORACT + Debug monitor active bit + 8 + 1 + + + PENDSVACT + PendSV exception active + bit + 10 + 1 + + + SYSTICKACT + SysTick exception active + bit + 11 + 1 + + + USGFAULTPENDED + Usage fault exception pending + bit + 12 + 1 + + + MEMFAULTPENDED + Memory management fault exception + pending bit + 13 + 1 + + + BUSFAULTPENDED + Bus fault exception pending + bit + 14 + 1 + + + SVCALLPENDED + SVC call pending bit + 15 + 1 + + + MEMFAULTENA + Memory management fault enable + bit + 16 + 1 + + + BUSFAULTENA + Bus fault enable bit + 17 + 1 + + + USGFAULTENA + Usage fault enable bit + 18 + 1 + + + + + CFSR_UFSR_BFSR_MMFSR + CFSR_UFSR_BFSR_MMFSR + Configurable fault status + register + 0x28 + 0x20 + read-write + 0x00000000 + + + IACCVIOL + IACCVIOL + 0 + 1 + + + DACCVIOL + DACCVIOL + 1 + 1 + + + MUNSTKERR + MUNSTKERR + 3 + 1 + + + MSTKERR + MSTKERR + 4 + 1 + + + MLSPERR + MLSPERR + 5 + 1 + + + MMARVALID + MMARVALID + 7 + 1 + + + IBUSERR + Instruction bus error + 8 + 1 + + + PRECISERR + Precise data bus error + 9 + 1 + + + IMPRECISERR + Imprecise data bus error + 10 + 1 + + + UNSTKERR + Bus fault on unstacking for a return + from exception + 11 + 1 + + + STKERR + Bus fault on stacking for exception + entry + 12 + 1 + + + LSPERR + Bus fault on floating-point lazy state + preservation + 13 + 1 + + + BFARVALID + Bus Fault Address Register (BFAR) valid + flag + 15 + 1 + + + UNDEFINSTR + Undefined instruction usage + fault + 16 + 1 + + + INVSTATE + Invalid state usage fault + 17 + 1 + + + INVPC + Invalid PC load usage + fault + 18 + 1 + + + NOCP + No coprocessor usage + fault. + 19 + 1 + + + UNALIGNED + Unaligned access usage + fault + 24 + 1 + + + DIVBYZERO + Divide by zero usage fault + 25 + 1 + + + + + HFSR + HFSR + Hard fault status register + 0x2C + 0x20 + read-write + 0x00000000 + + + VECTTBL + Vector table hard fault + 1 + 1 + + + FORCED + Forced hard fault + 30 + 1 + + + DEBUG_VT + Reserved for Debug use + 31 + 1 + + + + + MMFAR + MMFAR + Memory management fault address + register + 0x34 + 0x20 + read-write + 0x00000000 + + + MMFAR + Memory management fault + address + 0 + 32 + + + + + BFAR + BFAR + Bus fault address register + 0x38 + 0x20 + read-write + 0x00000000 + + + BFAR + Bus fault address + 0 + 32 + + + + + + + STK + SysTick timer + STK + 0xE000E010 + + 0x0 + 0x11 + registers + + + + CTRL + CTRL + SysTick control and status + register + 0x0 + 0x20 + read-write + 0X00000000 + + + ENABLE + Counter enable + 0 + 1 + + + TICKINT + SysTick exception request + enable + 1 + 1 + + + CLKSOURCE + Clock source selection + 2 + 1 + + + COUNTFLAG + COUNTFLAG + 16 + 1 + + + + + LOAD_ + LOAD_ + SysTick reload value register + 0x4 + 0x20 + read-write + 0X00000000 + + + RELOAD + RELOAD value + 0 + 24 + + + + + VAL + VAL + SysTick current value register + 0x8 + 0x20 + read-write + 0X00000000 + + + CURRENT + Current counter value + 0 + 24 + + + + + CALIB + CALIB + SysTick calibration value + register + 0xC + 0x20 + read-write + 0X00000000 + + + TENMS + Calibration value + 0 + 24 + + + + + + + diff --git a/sys/STM32F446.svd b/sys/STM32F446.svd new file mode 100644 index 0000000..2b729bb --- /dev/null +++ b/sys/STM32F446.svd @@ -0,0 +1,56913 @@ + + + + STM32F446 + 1.9 + STM32F446 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 0x20 + 0x0 + 0xFFFFFFFF + + + DCMI + Digital camera interface + DCMI + 0x50050000 + + 0x0 + 0x400 + registers + + + DCMI + DCMI global interrupt + 78 + + + + CR + CR + control register 1 + 0x0 + 0x20 + 0x0000 + + + CAPTURE + Capture enable + 0 + 1 + read-only + + + CM + Capture mode + 1 + 1 + read-write + + + CROP + Crop feature + 2 + 1 + read-write + + + JPEG + JPEG format + 3 + 1 + read-write + + + ESS + Embedded synchronization + select + 4 + 1 + read-write + + + PCKPOL + Pixel clock polarity + 5 + 1 + read-write + + + HSPOL + Horizontal synchronization + polarity + 6 + 1 + read-write + + + VSPOL + Vertical synchronization + polarity + 7 + 1 + read-write + + + EDM + Extended data mode + 10 + 2 + read-write + + + ENABLE + DCMI enable + 14 + 1 + read-write + + + BSM + Byte Select mode + 16 + 2 + read-only + + + OEBS + Odd/Even Byte Select + 18 + 1 + read-only + + + LSM + Line Select mode + 19 + 1 + read-only + + + OELS + Odd/Even Line Select + 20 + 1 + read-only + + + FCRC + Frame capture rate control + 8 + 2 + read-write + + + + + SR + SR + status register + 0x4 + 0x20 + read-only + 0x0000 + + + FNE + FIFO not empty + 2 + 1 + + + VSYNC + VSYNC + 1 + 1 + + + HSYNC + HSYNC + 0 + 1 + + + + + RIS + RIS + raw interrupt status register + 0x8 + 0x20 + read-only + 0x0000 + + + LINE_RIS + Line raw interrupt status + 4 + 1 + + + VSYNC_RIS + VSYNC raw interrupt status + 3 + 1 + + + ERR_RIS + Synchronization error raw interrupt + status + 2 + 1 + + + OVR_RIS + Overrun raw interrupt + status + 1 + 1 + + + FRAME_RIS + Capture complete raw interrupt + status + 0 + 1 + + + + + IER + IER + interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + LINE_IE + Line interrupt enable + 4 + 1 + + + VSYNC_IE + VSYNC interrupt enable + 3 + 1 + + + ERR_IE + Synchronization error interrupt + enable + 2 + 1 + + + OVR_IE + Overrun interrupt enable + 1 + 1 + + + FRAME_IE + Capture complete interrupt + enable + 0 + 1 + + + + + MIS + MIS + masked interrupt status + register + 0x10 + 0x20 + read-only + 0x0000 + + + LINE_MIS + Line masked interrupt + status + 4 + 1 + + + VSYNC_MIS + VSYNC masked interrupt + status + 3 + 1 + + + ERR_MIS + Synchronization error masked interrupt + status + 2 + 1 + + + OVR_MIS + Overrun masked interrupt + status + 1 + 1 + + + FRAME_MIS + Capture complete masked interrupt + status + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x14 + 0x20 + write-only + 0x0000 + + + LINE_ISC + line interrupt status + clear + 4 + 1 + + + VSYNC_ISC + Vertical synch interrupt status + clear + 3 + 1 + + + ERR_ISC + Synchronization error interrupt status + clear + 2 + 1 + + + OVR_ISC + Overrun interrupt status + clear + 1 + 1 + + + FRAME_ISC + Capture complete interrupt status + clear + 0 + 1 + + + + + ESCR + ESCR + embedded synchronization code + register + 0x18 + 0x20 + read-write + 0x0000 + + + FEC + Frame end delimiter code + 24 + 8 + + + LEC + Line end delimiter code + 16 + 8 + + + LSC + Line start delimiter code + 8 + 8 + + + FSC + Frame start delimiter code + 0 + 8 + + + + + ESUR + ESUR + embedded synchronization unmask + register + 0x1C + 0x20 + read-write + 0x0000 + + + FEU + Frame end delimiter unmask + 24 + 8 + + + LEU + Line end delimiter unmask + 16 + 8 + + + LSU + Line start delimiter + unmask + 8 + 8 + + + FSU + Frame start delimiter + unmask + 0 + 8 + + + + + CWSTRT + CWSTRT + crop window start + 0x20 + 0x20 + read-write + 0x0000 + + + VST + Vertical start line count + 16 + 13 + + + HOFFCNT + Horizontal offset count + 0 + 14 + + + + + CWSIZE + CWSIZE + crop window size + 0x24 + 0x20 + read-write + 0x0000 + + + VLINE + Vertical line count + 16 + 14 + + + CAPCNT + Capture count + 0 + 14 + + + + + DR + DR + data register + 0x28 + 0x20 + read-only + 0x0000 + + + Byte3 + Data byte 3 + 24 + 8 + + + Byte2 + Data byte 2 + 16 + 8 + + + Byte1 + Data byte 1 + 8 + 8 + + + Byte0 + Data byte 0 + 0 + 8 + + + + + + + FMC + Flexible memory controller + FSMC + 0xA0000000 + + 0x0 + 0x400 + registers + + + FMC + FMC global interrupt + 48 + + + + BCR1 + BCR1 + SRAM/NOR-Flash chip-select control register + 1 + 0x0 + 0x20 + read-write + 0x000030D0 + + + CCLKEN + CCLKEN + 20 + 1 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR1 + BTR1 + SRAM/NOR-Flash chip-select timing register + 1 + 0x4 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR2 + BCR2 + SRAM/NOR-Flash chip-select control register + 2 + 0x8 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR2 + BTR2 + SRAM/NOR-Flash chip-select timing register + 2 + 0xC + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR3 + BCR3 + SRAM/NOR-Flash chip-select control register + 3 + 0x10 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR3 + BTR3 + SRAM/NOR-Flash chip-select timing register + 3 + 0x14 + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BCR4 + BCR4 + SRAM/NOR-Flash chip-select control register + 4 + 0x18 + 0x20 + read-write + 0x000030D0 + + + CBURSTRW + CBURSTRW + 19 + 1 + + + ASYNCWAIT + ASYNCWAIT + 15 + 1 + + + EXTMOD + EXTMOD + 14 + 1 + + + WAITEN + WAITEN + 13 + 1 + + + WREN + WREN + 12 + 1 + + + WAITCFG + WAITCFG + 11 + 1 + + + WRAPMOD + WRAPMOD + 10 + 1 + + + WAITPOL + WAITPOL + 9 + 1 + + + BURSTEN + BURSTEN + 8 + 1 + + + FACCEN + FACCEN + 6 + 1 + + + MWID + MWID + 4 + 2 + + + MTYP + MTYP + 2 + 2 + + + MUXEN + MUXEN + 1 + 1 + + + MBKEN + MBKEN + 0 + 1 + + + + + BTR4 + BTR4 + SRAM/NOR-Flash chip-select timing register + 4 + 0x1C + 0x20 + read-write + 0xFFFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + BUSTURN + BUSTURN + 16 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + PCR2 + PCR2 + PC Card/NAND Flash control register + 2 + 0x60 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR2 + SR2 + FIFO status and interrupt register + 2 + 0x64 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM2 + PMEM2 + Common memory space timing register + 2 + 0x68 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT2 + PATT2 + Attribute memory space timing register + 2 + 0x6C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR2 + ECCR2 + ECC result register 2 + 0x74 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR3 + PCR3 + PC Card/NAND Flash control register + 3 + 0x80 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR3 + SR3 + FIFO status and interrupt register + 3 + 0x84 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM3 + PMEM3 + Common memory space timing register + 3 + 0x88 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT3 + PATT3 + Attribute memory space timing register + 3 + 0x8C + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + ECCR3 + ECCR3 + ECC result register 3 + 0x94 + 0x20 + read-only + 0x00000000 + + + ECCx + ECCx + 0 + 32 + + + + + PCR4 + PCR4 + PC Card/NAND Flash control register + 4 + 0xA0 + 0x20 + read-write + 0x00000018 + + + ECCPS + ECCPS + 17 + 3 + + + TAR + TAR + 13 + 4 + + + TCLR + TCLR + 9 + 4 + + + ECCEN + ECCEN + 6 + 1 + + + PWID + PWID + 4 + 2 + + + PTYP + PTYP + 3 + 1 + + + PBKEN + PBKEN + 2 + 1 + + + PWAITEN + PWAITEN + 1 + 1 + + + + + SR4 + SR4 + FIFO status and interrupt register + 4 + 0xA4 + 0x20 + 0x00000040 + + + FEMPT + FEMPT + 6 + 1 + read-only + + + IFEN + IFEN + 5 + 1 + read-write + + + ILEN + ILEN + 4 + 1 + read-write + + + IREN + IREN + 3 + 1 + read-write + + + IFS + IFS + 2 + 1 + read-write + + + ILS + ILS + 1 + 1 + read-write + + + IRS + IRS + 0 + 1 + read-write + + + + + PMEM4 + PMEM4 + Common memory space timing register + 4 + 0xA8 + 0x20 + read-write + 0xFCFCFCFC + + + MEMHIZx + MEMHIZx + 24 + 8 + + + MEMHOLDx + MEMHOLDx + 16 + 8 + + + MEMWAITx + MEMWAITx + 8 + 8 + + + MEMSETx + MEMSETx + 0 + 8 + + + + + PATT4 + PATT4 + Attribute memory space timing register + 4 + 0xAC + 0x20 + read-write + 0xFCFCFCFC + + + ATTHIZx + ATTHIZx + 24 + 8 + + + ATTHOLDx + ATTHOLDx + 16 + 8 + + + ATTWAITx + ATTWAITx + 8 + 8 + + + ATTSETx + ATTSETx + 0 + 8 + + + + + PIO4 + PIO4 + I/O space timing register 4 + 0xB0 + 0x20 + read-write + 0xFCFCFCFC + + + IOHIZx + IOHIZx + 24 + 8 + + + IOHOLDx + IOHOLDx + 16 + 8 + + + IOWAITx + IOWAITx + 8 + 8 + + + IOSETx + IOSETx + 0 + 8 + + + + + BWTR1 + BWTR1 + SRAM/NOR-Flash write timing registers + 1 + 0x104 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR2 + BWTR2 + SRAM/NOR-Flash write timing registers + 2 + 0x10C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR3 + BWTR3 + SRAM/NOR-Flash write timing registers + 3 + 0x114 + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + BWTR4 + BWTR4 + SRAM/NOR-Flash write timing registers + 4 + 0x11C + 0x20 + read-write + 0x0FFFFFFF + + + ACCMOD + ACCMOD + 28 + 2 + + + DATLAT + DATLAT + 24 + 4 + + + CLKDIV + CLKDIV + 20 + 4 + + + DATAST + DATAST + 8 + 8 + + + ADDHLD + ADDHLD + 4 + 4 + + + ADDSET + ADDSET + 0 + 4 + + + + + SDCR1 + SDCR1 + SDRAM Control Register 1 + 0x140 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address + bits + 0 + 2 + + + NR + Number of row address bits + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + NB + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WP + Write protection + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + RBURST + Burst read + 12 + 1 + + + RPIPE + Read pipe + 13 + 2 + + + + + SDCR2 + SDCR2 + SDRAM Control Register 2 + 0x144 + 0x20 + read-write + 0x000002D0 + + + NC + Number of column address + bits + 0 + 2 + + + NR + Number of row address bits + 2 + 2 + + + MWID + Memory data bus width + 4 + 2 + + + NB + Number of internal banks + 6 + 1 + + + CAS + CAS latency + 7 + 2 + + + WP + Write protection + 9 + 1 + + + SDCLK + SDRAM clock configuration + 10 + 2 + + + RBURST + Burst read + 12 + 1 + + + RPIPE + Read pipe + 13 + 2 + + + + + SDTR1 + SDTR1 + SDRAM Timing register 1 + 0x148 + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to + Active + 0 + 4 + + + TXSR + Exit self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDTR2 + SDTR2 + SDRAM Timing register 2 + 0x14C + 0x20 + read-write + 0x0FFFFFFF + + + TMRD + Load Mode Register to + Active + 0 + 4 + + + TXSR + Exit self-refresh delay + 4 + 4 + + + TRAS + Self refresh time + 8 + 4 + + + TRC + Row cycle delay + 12 + 4 + + + TWR + Recovery delay + 16 + 4 + + + TRP + Row precharge delay + 20 + 4 + + + TRCD + Row to column delay + 24 + 4 + + + + + SDCMR + SDCMR + SDRAM Command Mode register + 0x150 + 0x20 + 0x00000000 + + + MODE + Command mode + 0 + 3 + write-only + + + CTB2 + Command target bank 2 + 3 + 1 + write-only + + + CTB1 + Command target bank 1 + 4 + 1 + write-only + + + NRFS + Number of Auto-refresh + 5 + 4 + read-write + + + MRD + Mode Register definition + 9 + 13 + read-write + + + + + SDRTR + SDRTR + SDRAM Refresh Timer register + 0x154 + 0x20 + 0x00000000 + + + CRE + Clear Refresh error flag + 0 + 1 + write-only + + + COUNT + Refresh Timer Count + 1 + 13 + read-write + + + REIE + RES Interrupt Enable + 14 + 1 + read-write + + + + + SDSR + SDSR + SDRAM Status register + 0x158 + 0x20 + read-only + 0x00000000 + + + RE + Refresh error flag + 0 + 1 + + + MODES1 + Status Mode for Bank 1 + 1 + 2 + + + MODES2 + Status Mode for Bank 2 + 3 + 2 + + + BUSY + Busy status + 5 + 1 + + + + + + + DBG + Debug support + DBG + 0xE0042000 + + 0x0 + 0x400 + registers + + + + DBGMCU_IDCODE + DBGMCU_IDCODE + IDCODE + 0x0 + 0x20 + read-only + 0x10006411 + + + DEV_ID + DEV_ID + 0 + 12 + + + REV_ID + REV_ID + 16 + 16 + + + + + DBGMCU_CR + DBGMCU_CR + Control Register + 0x4 + 0x20 + read-write + 0x00000000 + + + DBG_SLEEP + DBG_SLEEP + 0 + 1 + + + DBG_STOP + DBG_STOP + 1 + 1 + + + DBG_STANDBY + DBG_STANDBY + 2 + 1 + + + TRACE_IOEN + TRACE_IOEN + 5 + 1 + + + TRACE_MODE + TRACE_MODE + 6 + 2 + + + + + DBGMCU_APB1_FZ + DBGMCU_APB1_FZ + Debug MCU APB1 Freeze registe + 0x8 + 0x20 + read-write + 0x00000000 + + + DBG_TIM2_STOP + DBG_TIM2_STOP + 0 + 1 + + + DBG_TIM3_STOP + DBG_TIM3 _STOP + 1 + 1 + + + DBG_TIM4_STOP + DBG_TIM4_STOP + 2 + 1 + + + DBG_TIM5_STOP + DBG_TIM5_STOP + 3 + 1 + + + DBG_TIM6_STOP + DBG_TIM6_STOP + 4 + 1 + + + DBG_TIM7_STOP + DBG_TIM7_STOP + 5 + 1 + + + DBG_TIM12_STOP + DBG_TIM12_STOP + 6 + 1 + + + DBG_TIM13_STOP + DBG_TIM13_STOP + 7 + 1 + + + DBG_TIM14_STOP + DBG_TIM14_STOP + 8 + 1 + + + DBG_RTC_STOP + RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + DBG_WWDG_STOP + 11 + 1 + + + DBG_IWDEG_STOP + DBG_IWDEG_STOP + 12 + 1 + + + DBG_J2C1_SMBUS_TIMEOUT + DBG_J2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_J2C2_SMBUS_TIMEOUT + DBG_J2C2_SMBUS_TIMEOUT + 22 + 1 + + + DBG_J2C3SMBUS_TIMEOUT + DBG_J2C3SMBUS_TIMEOUT + 23 + 1 + + + DBG_I2CFMP_SMBUS_TIMEOUT + SMBUS timeout mode stopped when Core is + halted + 24 + 1 + + + DBG_CAN1_STOP + DBG_CAN1_STOP + 25 + 1 + + + DBG_CAN2_STOP + DBG_CAN2_STOP + 26 + 1 + + + + + DBGMCU_APB2_FZ + DBGMCU_APB2_FZ + Debug MCU APB2 Freeze registe + 0xC + 0x20 + read-write + 0x00000000 + + + DBG_TIM1_STOP + TIM1 counter stopped when core is + halted + 0 + 1 + + + DBG_TIM8_STOP + TIM8 counter stopped when core is + halted + 1 + 1 + + + DBG_TIM9_STOP + TIM9 counter stopped when core is + halted + 16 + 1 + + + DBG_TIM10_STOP + TIM10 counter stopped when core is + halted + 17 + 1 + + + DBG_TIM11_STOP + TIM11 counter stopped when core is + halted + 18 + 1 + + + + + + + DMA2 + DMA controller + DMA + 0x40026400 + + 0x0 + 0x400 + registers + + + DMA2_Stream0 + DMA2 Stream0 global interrupt + 56 + + + DMA2_Stream1 + DMA2 Stream1 global interrupt + 57 + + + DMA2_Stream2 + DMA2 Stream2 global interrupt + 58 + + + DMA2_Stream3 + DMA2 Stream3 global interrupt + 59 + + + DMA2_Stream4 + DMA2 Stream4 global interrupt + 60 + + + DMA2_Stream5 + DMA2 Stream5 global interrupt + 68 + + + DMA2_Stream6 + DMA2 Stream6 global interrupt + 69 + + + DMA2_Stream7 + DMA2 Stream7 global interrupt + 70 + + + + LISR + LISR + low interrupt status register + 0x0 + 0x20 + read-only + 0x00000000 + + + TCIF3 + Stream x transfer complete interrupt + flag (x = 3..0) + 27 + 1 + + + HTIF3 + Stream x half transfer interrupt flag + (x=3..0) + 26 + 1 + + + TEIF3 + Stream x transfer error interrupt flag + (x=3..0) + 25 + 1 + + + DMEIF3 + Stream x direct mode error interrupt + flag (x=3..0) + 24 + 1 + + + FEIF3 + Stream x FIFO error interrupt flag + (x=3..0) + 22 + 1 + + + TCIF2 + Stream x transfer complete interrupt + flag (x = 3..0) + 21 + 1 + + + HTIF2 + Stream x half transfer interrupt flag + (x=3..0) + 20 + 1 + + + TEIF2 + Stream x transfer error interrupt flag + (x=3..0) + 19 + 1 + + + DMEIF2 + Stream x direct mode error interrupt + flag (x=3..0) + 18 + 1 + + + FEIF2 + Stream x FIFO error interrupt flag + (x=3..0) + 16 + 1 + + + TCIF1 + Stream x transfer complete interrupt + flag (x = 3..0) + 11 + 1 + + + HTIF1 + Stream x half transfer interrupt flag + (x=3..0) + 10 + 1 + + + TEIF1 + Stream x transfer error interrupt flag + (x=3..0) + 9 + 1 + + + DMEIF1 + Stream x direct mode error interrupt + flag (x=3..0) + 8 + 1 + + + FEIF1 + Stream x FIFO error interrupt flag + (x=3..0) + 6 + 1 + + + TCIF0 + Stream x transfer complete interrupt + flag (x = 3..0) + 5 + 1 + + + HTIF0 + Stream x half transfer interrupt flag + (x=3..0) + 4 + 1 + + + TEIF0 + Stream x transfer error interrupt flag + (x=3..0) + 3 + 1 + + + DMEIF0 + Stream x direct mode error interrupt + flag (x=3..0) + 2 + 1 + + + FEIF0 + Stream x FIFO error interrupt flag + (x=3..0) + 0 + 1 + + + + + HISR + HISR + high interrupt status register + 0x4 + 0x20 + read-only + 0x00000000 + + + TCIF7 + Stream x transfer complete interrupt + flag (x=7..4) + 27 + 1 + + + HTIF7 + Stream x half transfer interrupt flag + (x=7..4) + 26 + 1 + + + TEIF7 + Stream x transfer error interrupt flag + (x=7..4) + 25 + 1 + + + DMEIF7 + Stream x direct mode error interrupt + flag (x=7..4) + 24 + 1 + + + FEIF7 + Stream x FIFO error interrupt flag + (x=7..4) + 22 + 1 + + + TCIF6 + Stream x transfer complete interrupt + flag (x=7..4) + 21 + 1 + + + HTIF6 + Stream x half transfer interrupt flag + (x=7..4) + 20 + 1 + + + TEIF6 + Stream x transfer error interrupt flag + (x=7..4) + 19 + 1 + + + DMEIF6 + Stream x direct mode error interrupt + flag (x=7..4) + 18 + 1 + + + FEIF6 + Stream x FIFO error interrupt flag + (x=7..4) + 16 + 1 + + + TCIF5 + Stream x transfer complete interrupt + flag (x=7..4) + 11 + 1 + + + HTIF5 + Stream x half transfer interrupt flag + (x=7..4) + 10 + 1 + + + TEIF5 + Stream x transfer error interrupt flag + (x=7..4) + 9 + 1 + + + DMEIF5 + Stream x direct mode error interrupt + flag (x=7..4) + 8 + 1 + + + FEIF5 + Stream x FIFO error interrupt flag + (x=7..4) + 6 + 1 + + + TCIF4 + Stream x transfer complete interrupt + flag (x=7..4) + 5 + 1 + + + HTIF4 + Stream x half transfer interrupt flag + (x=7..4) + 4 + 1 + + + TEIF4 + Stream x transfer error interrupt flag + (x=7..4) + 3 + 1 + + + DMEIF4 + Stream x direct mode error interrupt + flag (x=7..4) + 2 + 1 + + + FEIF4 + Stream x FIFO error interrupt flag + (x=7..4) + 0 + 1 + + + + + LIFCR + LIFCR + low interrupt flag clear + register + 0x8 + 0x20 + read-write + 0x00000000 + + + CTCIF3 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 27 + 1 + + + CHTIF3 + Stream x clear half transfer interrupt + flag (x = 3..0) + 26 + 1 + + + CTEIF3 + Stream x clear transfer error interrupt + flag (x = 3..0) + 25 + 1 + + + CDMEIF3 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 24 + 1 + + + CFEIF3 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 22 + 1 + + + CTCIF2 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 21 + 1 + + + CHTIF2 + Stream x clear half transfer interrupt + flag (x = 3..0) + 20 + 1 + + + CTEIF2 + Stream x clear transfer error interrupt + flag (x = 3..0) + 19 + 1 + + + CDMEIF2 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 18 + 1 + + + CFEIF2 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 16 + 1 + + + CTCIF1 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 11 + 1 + + + CHTIF1 + Stream x clear half transfer interrupt + flag (x = 3..0) + 10 + 1 + + + CTEIF1 + Stream x clear transfer error interrupt + flag (x = 3..0) + 9 + 1 + + + CDMEIF1 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 8 + 1 + + + CFEIF1 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 6 + 1 + + + CTCIF0 + Stream x clear transfer complete + interrupt flag (x = 3..0) + 5 + 1 + + + CHTIF0 + Stream x clear half transfer interrupt + flag (x = 3..0) + 4 + 1 + + + CTEIF0 + Stream x clear transfer error interrupt + flag (x = 3..0) + 3 + 1 + + + CDMEIF0 + Stream x clear direct mode error + interrupt flag (x = 3..0) + 2 + 1 + + + CFEIF0 + Stream x clear FIFO error interrupt flag + (x = 3..0) + 0 + 1 + + + + + HIFCR + HIFCR + high interrupt flag clear + register + 0xC + 0x20 + read-write + 0x00000000 + + + CTCIF7 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 27 + 1 + + + CHTIF7 + Stream x clear half transfer interrupt + flag (x = 7..4) + 26 + 1 + + + CTEIF7 + Stream x clear transfer error interrupt + flag (x = 7..4) + 25 + 1 + + + CDMEIF7 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 24 + 1 + + + CFEIF7 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 22 + 1 + + + CTCIF6 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 21 + 1 + + + CHTIF6 + Stream x clear half transfer interrupt + flag (x = 7..4) + 20 + 1 + + + CTEIF6 + Stream x clear transfer error interrupt + flag (x = 7..4) + 19 + 1 + + + CDMEIF6 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 18 + 1 + + + CFEIF6 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 16 + 1 + + + CTCIF5 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 11 + 1 + + + CHTIF5 + Stream x clear half transfer interrupt + flag (x = 7..4) + 10 + 1 + + + CTEIF5 + Stream x clear transfer error interrupt + flag (x = 7..4) + 9 + 1 + + + CDMEIF5 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 8 + 1 + + + CFEIF5 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 6 + 1 + + + CTCIF4 + Stream x clear transfer complete + interrupt flag (x = 7..4) + 5 + 1 + + + CHTIF4 + Stream x clear half transfer interrupt + flag (x = 7..4) + 4 + 1 + + + CTEIF4 + Stream x clear transfer error interrupt + flag (x = 7..4) + 3 + 1 + + + CDMEIF4 + Stream x clear direct mode error + interrupt flag (x = 7..4) + 2 + 1 + + + CFEIF4 + Stream x clear FIFO error interrupt flag + (x = 7..4) + 0 + 1 + + + + + S0CR + S0CR + stream x configuration + register + 0x10 + 0x20 + read-write + 0x00000000 + + + CHSEL + Channel selection + 25 + 3 + + + MBURST + Memory burst transfer + configuration + 23 + 2 + + + PBURST + Peripheral burst transfer + configuration + 21 + 2 + + + CT + Current target (only in double buffer + mode) + 19 + 1 + + + DBM + Double buffer mode + 18 + 1 + + + PL + Priority level + 16 + 2 + + + PINCOS + Peripheral increment offset + size + 15 + 1 + + + MSIZE + Memory data size + 13 + 2 + + + PSIZE + Peripheral data size + 11 + 2 + + + MINC + Memory increment mode + 10 + 1 + + + PINC + Peripheral increment mode + 9 + 1 + + + CIRC + Circular mode + 8 + 1 + + + DIR + Data transfer direction + 6 + 2 + + + PFCTRL + Peripheral flow controller + 5 + 1 + + + TCIE + Transfer complete interrupt + enable + 4 + 1 + + + HTIE + Half transfer interrupt + enable + 3 + 1 + + + TEIE + Transfer error interrupt + enable + 2 + 1 + + + DMEIE + Direct mode error interrupt + enable + 1 + 1 + + + EN + Stream enable / flag stream ready when + read low + 0 + 1 + + + + + S0NDTR + S0NDTR + stream x number of data + register + 0x14 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data items to + transfer + 0 + 16 + + + + + S0PAR + S0PAR + stream x peripheral address + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + S0M0AR + S0M0AR + stream x memory 0 address + register + 0x1C + 0x20 + read-write + 0x00000000 + + + M0A + Memory 0 address + 0 + 32 + + + + + S0M1AR + S0M1AR + stream x memory 1 address + register + 0x20 + 0x20 + read-write + 0x00000000 + + + M1A + Memory 1 address (used in case of Double + buffer mode) + 0 + 32 + + + + + S0FCR + S0FCR + stream x FIFO control register + 0x24 + 0x20 + 0x00000021 + + + FEIE + FIFO error interrupt + enable + 7 + 1 + read-write + + + FS + FIFO status + 3 + 3 + read-only + + + DMDIS + Direct mode disable + 2 + 1 + read-write + + + FTH + FIFO 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Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 25 + 1 + + + PLLQ0 + Main PLL (PLL) division factor for USB + OTG FS, SDIO and random number generator + clocks + 24 + 1 + + + PLLSRC + Main PLL(PLL) and audio PLL (PLLI2S) + entry clock source + 22 + 1 + + + PLLP1 + Main PLL (PLL) division factor for main + system clock + 17 + 1 + + + PLLP0 + Main PLL (PLL) division factor for main + system clock + 16 + 1 + + + PLLN8 + Main PLL (PLL) multiplication factor for + VCO + 14 + 1 + + + PLLN7 + Main PLL (PLL) multiplication factor for + VCO + 13 + 1 + + + PLLN6 + Main PLL (PLL) multiplication factor for + VCO + 12 + 1 + + + PLLN5 + Main PLL (PLL) multiplication factor for + VCO + 11 + 1 + + + PLLN4 + Main PLL (PLL) multiplication factor for + VCO + 10 + 1 + + + PLLN3 + Main PLL (PLL) multiplication factor for + VCO + 9 + 1 + + + PLLN2 + Main PLL (PLL) multiplication factor for + VCO + 8 + 1 + + + PLLN1 + Main PLL (PLL) multiplication factor for + VCO + 7 + 1 + + + PLLN0 + Main PLL (PLL) multiplication factor for + VCO + 6 + 1 + + + PLLM5 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 5 + 1 + + + PLLM4 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 4 + 1 + + + PLLM3 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 3 + 1 + + + PLLM2 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 2 + 1 + + + PLLM1 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 1 + 1 + + + PLLM0 + Division factor for the main PLL (PLL) + and audio PLL (PLLI2S) input clock + 0 + 1 + + + + + CFGR + CFGR + clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCO2 + Microcontroller clock output + 2 + 30 + 2 + read-write + + + MCO2PRE + MCO2 prescaler + 27 + 3 + read-write + + + MCO1PRE + MCO1 prescaler + 24 + 3 + read-write + + + I2SSRC + I2S clock selection + 23 + 1 + read-write + + + MCO1 + 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interrupt clear + 18 + 1 + write-only + + + LSERDYC + LSE ready interrupt clear + 17 + 1 + write-only + + + LSIRDYC + LSI ready interrupt clear + 16 + 1 + write-only + + + PLLSAIRDYIE + PLLSAI Ready Interrupt + Enable + 14 + 1 + read-write + + + PLLI2SRDYIE + PLLI2S ready interrupt + enable + 13 + 1 + read-write + + + PLLRDYIE + Main PLL (PLL) ready interrupt + enable + 12 + 1 + read-write + + + HSERDYIE + HSE ready interrupt enable + 11 + 1 + read-write + + + HSIRDYIE + HSI ready interrupt enable + 10 + 1 + read-write + + + LSERDYIE + LSE ready interrupt enable + 9 + 1 + read-write + + + LSIRDYIE + LSI ready interrupt enable + 8 + 1 + read-write + + + CSSF + Clock security system interrupt + flag + 7 + 1 + read-only + + + PLLSAIRDYF + PLLSAI ready interrupt + flag + 6 + 1 + read-only + + + PLLI2SRDYF + PLLI2S ready interrupt + flag + 5 + 1 + read-only + + + PLLRDYF + Main PLL (PLL) ready interrupt + flag + 4 + 1 + read-only + + + HSERDYF + HSE ready interrupt flag + 3 + 1 + read-only + + + HSIRDYF + HSI ready interrupt flag + 2 + 1 + read-only + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + read-only + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + read-only + + + + + AHB1RSTR + AHB1RSTR + AHB1 peripheral reset register + 0x10 + 0x20 + read-write + 0x00000000 + + + OTGHSRST + USB OTG HS module reset + 29 + 1 + + + DMA2RST + DMA2 reset + 22 + 1 + + + DMA1RST + DMA2 reset + 21 + 1 + + + CRCRST + CRC reset + 12 + 1 + + + GPIOHRST + IO port H reset + 7 + 1 + + + GPIOGRST + IO port G reset + 6 + 1 + + + GPIOFRST + IO port F reset + 5 + 1 + + + GPIOERST + IO port E reset + 4 + 1 + + + GPIODRST + IO port D reset + 3 + 1 + + + GPIOCRST + IO port C reset + 2 + 1 + + + GPIOBRST + IO port B reset + 1 + 1 + + + GPIOARST + IO port A reset + 0 + 1 + + + + + AHB2RSTR + AHB2RSTR + AHB2 peripheral reset register + 0x14 + 0x20 + read-write + 0x00000000 + + + OTGFSRST + USB OTG FS module reset + 7 + 1 + + + DCMIRST + Camera interface reset + 0 + 1 + + + + + AHB3RSTR + AHB3RSTR + AHB3 peripheral reset register + 0x18 + 0x20 + read-write + 0x00000000 + + + FMCRST + Flexible memory controller module + reset + 0 + 1 + + + QSPIRST + QUADSPI module reset + 1 + 1 + + + + + APB1RSTR + APB1RSTR + APB1 peripheral reset register + 0x20 + 0x20 + read-write + 0x00000000 + + + TIM2RST + TIM2 reset + 0 + 1 + + + TIM3RST + TIM3 reset + 1 + 1 + + + TIM4RST + TIM4 reset + 2 + 1 + + + TIM5RST + TIM5 reset + 3 + 1 + + + TIM6RST + TIM6 reset + 4 + 1 + + + TIM7RST + TIM7 reset + 5 + 1 + + + TIM12RST + TIM12 reset + 6 + 1 + + + TIM13RST + TIM13 reset + 7 + 1 + + + TIM14RST + TIM14 reset + 8 + 1 + + + WWDGRST + Window watchdog reset + 11 + 1 + + + SPI2RST + SPI 2 reset + 14 + 1 + + + SPI3RST + SPI 3 reset + 15 + 1 + + + SPDIFRST + SPDIF-IN reset + 16 + 1 + + + UART2RST + USART 2 reset + 17 + 1 + + + UART3RST + USART 3 reset + 18 + 1 + + + UART4RST + USART 4 reset + 19 + 1 + + + UART5RST + USART 5 reset + 20 + 1 + + + I2C1RST + I2C 1 reset + 21 + 1 + + + I2C2RST + I2C 2 reset + 22 + 1 + + + I2C3RST + I2C3 reset + 23 + 1 + + + I2CFMP1RST + I2CFMP1 reset + 24 + 1 + + + CAN1RST + CAN1 reset + 25 + 1 + + + CAN2RST + CAN2 reset + 26 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DACRST + DAC reset + 29 + 1 + + + + + APB2RSTR + APB2RSTR + APB2 peripheral reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + TIM1RST + TIM1 reset + 0 + 1 + + + TIM8RST + TIM8 reset + 1 + 1 + + + USART1RST + USART1 reset + 4 + 1 + + + USART6RST + USART6 reset + 5 + 1 + + + ADCRST + ADC interface reset (common to all + ADCs) + 8 + 1 + + + SDIORST + SDIO reset + 11 + 1 + + + SPI1RST + SPI 1 reset + 12 + 1 + + + SPI4RST + SPI4 reset + 13 + 1 + + + SYSCFGRST + System configuration controller + reset + 14 + 1 + + + TIM9RST + TIM9 reset + 16 + 1 + + + TIM10RST + TIM10 reset + 17 + 1 + + + TIM11RST + TIM11 reset + 18 + 1 + + + SAI1RST + SAI1 reset + 22 + 1 + + + SAI2RST + SAI2 reset + 23 + 1 + + + + + AHB1ENR + AHB1ENR + AHB1 peripheral clock register + 0x30 + 0x20 + read-write + 0x00100000 + + + OTGHSULPIEN + USB OTG HSULPI clock + enable + 30 + 1 + + + OTGHSEN + USB OTG HS clock enable + 29 + 1 + + + DMA2EN + DMA2 clock enable + 22 + 1 + + + DMA1EN + DMA1 clock enable + 21 + 1 + + + BKPSRAMEN + Backup SRAM interface clock + enable + 18 + 1 + + + CRCEN + CRC clock enable + 12 + 1 + + + GPIOHEN + IO port H clock enable + 7 + 1 + + + GPIOGEN + IO port G clock enable + 6 + 1 + + + GPIOFEN + IO port F clock enable + 5 + 1 + + + GPIOEEN + IO port E clock enable + 4 + 1 + + + GPIODEN + IO port D clock enable + 3 + 1 + + + GPIOCEN + IO port C clock enable + 2 + 1 + + + GPIOBEN + IO port B clock enable + 1 + 1 + + + GPIOAEN + IO port A clock enable + 0 + 1 + + + + + AHB2ENR + AHB2ENR + AHB2 peripheral clock enable + register + 0x34 + 0x20 + read-write + 0x00000000 + + + OTGFSEN + USB OTG FS clock enable + 7 + 1 + + + DCMIEN + Camera interface enable + 0 + 1 + + + + + AHB3ENR + AHB3ENR + AHB3 peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + FMCEN + Flexible memory controller module clock + enable + 0 + 1 + + + QSPIEN + QUADSPI memory controller module clock + enable + 1 + 1 + + + + + APB1ENR + APB1ENR + APB1 peripheral clock enable + register + 0x40 + 0x20 + read-write + 0x00000000 + + + TIM2EN + TIM2 clock enable + 0 + 1 + + + TIM3EN + TIM3 clock enable + 1 + 1 + + + TIM4EN + TIM4 clock enable + 2 + 1 + + + TIM5EN + TIM5 clock enable + 3 + 1 + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + TIM7EN + TIM7 clock enable + 5 + 1 + + + TIM12EN + TIM12 clock enable + 6 + 1 + + + TIM13EN + TIM13 clock enable + 7 + 1 + + + TIM14EN + TIM14 clock enable + 8 + 1 + + + WWDGEN + Window watchdog clock + enable + 11 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + SPI3EN + SPI3 clock enable + 15 + 1 + + + SPDIFEN + SPDIF-IN clock enable + 16 + 1 + + + USART2EN + USART 2 clock enable + 17 + 1 + + + USART3EN + USART3 clock enable + 18 + 1 + + + UART4EN + UART4 clock enable + 19 + 1 + + + UART5EN + UART5 clock enable + 20 + 1 + + + I2C1EN + I2C1 clock enable + 21 + 1 + + + I2C2EN + I2C2 clock enable + 22 + 1 + + + I2C3EN + I2C3 clock enable + 23 + 1 + + + I2CFMP1EN + I2CFMP1 clock enable + 24 + 1 + + + CAN1EN + CAN 1 clock enable + 25 + 1 + + + CAN2EN + CAN 2 clock enable + 26 + 1 + + + CEC + CEC interface clock enable + 27 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DACEN + DAC interface clock enable + 29 + 1 + + + + + APB2ENR + APB2ENR + APB2 peripheral clock enable + register + 0x44 + 0x20 + read-write + 0x00000000 + + + TIM1EN + TIM1 clock enable + 0 + 1 + + + TIM8EN + TIM8 clock enable + 1 + 1 + + + USART1EN + USART1 clock enable + 4 + 1 + + + USART6EN + USART6 clock enable + 5 + 1 + + + ADC1EN + ADC1 clock enable + 8 + 1 + + + ADC2EN + ADC2 clock enable + 9 + 1 + + + ADC3EN + ADC3 clock enable + 10 + 1 + + + SDIOEN + SDIO clock enable + 11 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + SPI4ENR + SPI4 clock enable + 13 + 1 + + + SYSCFGEN + System configuration controller clock + enable + 14 + 1 + + + TIM9EN + TIM9 clock enable + 16 + 1 + + + TIM10EN + TIM10 clock enable + 17 + 1 + + + TIM11EN + TIM11 clock enable + 18 + 1 + + + SAI1EN + SAI1 clock enable + 22 + 1 + + + SAI2EN + SAI2 clock enable + 23 + 1 + + + + + AHB1LPENR + AHB1LPENR + AHB1 peripheral clock enable in low power + mode register + 0x50 + 0x20 + read-write + 0x7E6791FF + + + GPIOALPEN + IO port A clock enable during sleep + mode + 0 + 1 + + + GPIOBLPEN + IO port B clock enable during Sleep + mode + 1 + 1 + + + GPIOCLPEN + IO port C clock enable during Sleep + mode + 2 + 1 + + + GPIODLPEN + IO port D clock enable during Sleep + mode + 3 + 1 + + + GPIOELPEN + IO port E clock enable during Sleep + mode + 4 + 1 + + + GPIOFLPEN + IO port F clock enable during Sleep + mode + 5 + 1 + + + GPIOGLPEN + IO port G clock enable during Sleep + mode + 6 + 1 + + + GPIOHLPEN + IO port H clock enable during Sleep + mode + 7 + 1 + + + CRCLPEN + CRC clock enable during Sleep + mode + 12 + 1 + + + FLITFLPEN + Flash interface clock enable during + Sleep mode + 15 + 1 + + + SRAM1LPEN + SRAM 1interface clock enable during + Sleep mode + 16 + 1 + + + SRAM2LPEN + SRAM 2 interface clock enable during + Sleep mode + 17 + 1 + + + BKPSRAMLPEN + Backup SRAM interface clock enable + during Sleep mode + 18 + 1 + + + DMA1LPEN + DMA1 clock enable during Sleep + mode + 21 + 1 + + + DMA2LPEN + DMA2 clock enable during Sleep + mode + 22 + 1 + + + OTGHSLPEN + USB OTG HS clock enable during Sleep + mode + 29 + 1 + + + OTGHSULPILPEN + USB OTG HS ULPI clock enable during + Sleep mode + 30 + 1 + + + + + AHB2LPENR + AHB2LPENR + AHB2 peripheral clock enable in low power + mode register + 0x54 + 0x20 + read-write + 0x000000F1 + + + OTGFSLPEN + USB OTG FS clock enable during Sleep + mode + 7 + 1 + + + DCMILPEN + Camera interface enable during Sleep + mode + 0 + 1 + + + + + AHB3LPENR + AHB3LPENR + AHB3 peripheral clock enable in low power + mode register + 0x58 + 0x20 + read-write + 0x00000001 + + + FMCLPEN + Flexible memory controller module clock + enable during Sleep mode + 0 + 1 + + + QSPILPEN + QUADSPI memory controller module clock + enable during Sleep mode + 1 + 1 + + + + + APB1LPENR + APB1LPENR + APB1 peripheral clock enable in low power + mode register + 0x60 + 0x20 + read-write + 0x36FEC9FF + + + TIM2LPEN + TIM2 clock enable during Sleep + mode + 0 + 1 + + + TIM3LPEN + TIM3 clock enable during Sleep + mode + 1 + 1 + + + TIM4LPEN + TIM4 clock enable during Sleep + mode + 2 + 1 + + + TIM5LPEN + TIM5 clock enable during Sleep + mode + 3 + 1 + + + TIM6LPEN + TIM6 clock enable during Sleep + mode + 4 + 1 + + + TIM7LPEN + TIM7 clock enable during Sleep + mode + 5 + 1 + + + TIM12LPEN + TIM12 clock enable during Sleep + mode + 6 + 1 + + + TIM13LPEN + TIM13 clock enable during Sleep + mode + 7 + 1 + + + TIM14LPEN + TIM14 clock enable during Sleep + mode + 8 + 1 + + + WWDGLPEN + Window watchdog clock enable during + Sleep mode + 11 + 1 + + + SPI2LPEN + SPI2 clock enable during Sleep + mode + 14 + 1 + + + SPI3LPEN + SPI3 clock enable during Sleep + mode + 15 + 1 + + + SPDIFLPEN + SPDIF clock enable during Sleep + mode + 16 + 1 + + + USART2LPEN + USART2 clock enable during Sleep + mode + 17 + 1 + + + USART3LPEN + USART3 clock enable during Sleep + mode + 18 + 1 + + + UART4LPEN + UART4 clock enable during Sleep + mode + 19 + 1 + + + UART5LPEN + UART5 clock enable during Sleep + mode + 20 + 1 + + + I2C1LPEN + I2C1 clock enable during Sleep + mode + 21 + 1 + + + I2C2LPEN + I2C2 clock enable during Sleep + mode + 22 + 1 + + + I2C3LPEN + I2C3 clock enable during Sleep + mode + 23 + 1 + + + I2CFMP1LPEN + I2CFMP1 clock enable during Sleep + mode + 24 + 1 + + + CAN1LPEN + CAN 1 clock enable during Sleep + mode + 25 + 1 + + + CAN2LPEN + CAN 2 clock enable during Sleep + mode + 26 + 1 + + + CECLPEN + CEC clock enable during Sleep + mode + 27 + 1 + + + PWRLPEN + Power interface clock enable during + Sleep mode + 28 + 1 + + + DACLPEN + DAC interface clock enable during Sleep + mode + 29 + 1 + + + + + APB2LPENR + APB2LPENR + APB2 peripheral clock enabled in low power + mode register + 0x64 + 0x20 + read-write + 0x00075F33 + + + TIM1LPEN + TIM1 clock enable during Sleep + mode + 0 + 1 + + + TIM8LPEN + TIM8 clock enable during Sleep + mode + 1 + 1 + + + USART1LPEN + USART1 clock enable during Sleep + mode + 4 + 1 + + + USART6LPEN + USART6 clock enable during Sleep + mode + 5 + 1 + + + ADC1LPEN + ADC1 clock enable during Sleep + mode + 8 + 1 + + + ADC2LPEN + ADC2 clock enable during Sleep + mode + 9 + 1 + + + ADC3LPEN + ADC 3 clock enable during Sleep + mode + 10 + 1 + + + SDIOLPEN + SDIO clock enable during Sleep + mode + 11 + 1 + + + SPI1LPEN + SPI 1 clock enable during Sleep + mode + 12 + 1 + + + SPI4LPEN + SPI 4 clock enable during Sleep + mode + 13 + 1 + + + SYSCFGLPEN + System configuration controller clock + enable during Sleep mode + 14 + 1 + + + TIM9LPEN + TIM9 clock enable during sleep + mode + 16 + 1 + + + TIM10LPEN + TIM10 clock enable during Sleep + mode + 17 + 1 + + + TIM11LPEN + TIM11 clock enable during Sleep + mode + 18 + 1 + + + SAI1LPEN + SAI1 clock enable + 22 + 1 + + + SAI2LPEN + SAI2 clock enable + 23 + 1 + + + + + BDCR + BDCR + Backup domain control register + 0x70 + 0x20 + 0x00000000 + + + BDRST + Backup domain software + reset + 16 + 1 + read-write + + + RTCEN + RTC clock enable + 15 + 1 + read-write + + + RTCSEL + RTC clock source selection + 8 + 2 + read-write + + + LSEMOD + External low-speed oscillator + mode + 3 + 1 + read-write + + + LSEBYP + External low-speed oscillator + bypass + 2 + 1 + read-write + + + LSERDY + External low-speed oscillator + ready + 1 + 1 + read-only + + + LSEON + External low-speed oscillator + enable + 0 + 1 + read-write + + + + + CSR + CSR + clock control & status + register + 0x74 + 0x20 + 0x0E000000 + + + LPWRRSTF + Low-power reset flag + 31 + 1 + read-write + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + read-write + + + WDGRSTF + Independent watchdog reset + flag + 29 + 1 + read-write + + + SFTRSTF + Software reset flag + 28 + 1 + read-write + + + PORRSTF + POR/PDR reset flag + 27 + 1 + read-write + + + PADRSTF + PIN reset flag + 26 + 1 + read-write + + + BORRSTF + BOR reset flag + 25 + 1 + read-write + + + RMVF + Remove reset flag + 24 + 1 + read-write + + + LSIRDY + Internal low-speed oscillator + ready + 1 + 1 + read-only + + + LSION + Internal low-speed oscillator + enable + 0 + 1 + read-write + + + + + SSCGR + SSCGR + spread spectrum clock generation + register + 0x80 + 0x20 + read-write + 0x00000000 + + + SSCGEN + Spread spectrum modulation + enable + 31 + 1 + + + SPREADSEL + Spread Select + 30 + 1 + + + INCSTEP + Incrementation step + 13 + 15 + + + MODPER + Modulation period + 0 + 13 + + + + + PLLI2SCFGR + PLLI2SCFGR + PLLI2S configuration register + 0x84 + 0x20 + read-write + 0x20003000 + + + PLLI2SM + Division factor for audio PLL (PLLI2S) + input clock + 0 + 6 + + + PLLI2SN + PLLI2S multiplication factor for + VCO + 6 + 9 + + + PLLI2SP + PLLI2S division factor for SPDIF-IN + clock + 16 + 2 + + + PLLI2SQ + PLLI2S division factor for SAI1 + clock + 24 + 4 + + + PLLI2SR + PLLI2S division factor for I2S + clocks + 28 + 3 + + + + + PLLSAICFGR + PLLSAICFGR + PLL configuration register + 0x88 + 0x20 + read-write + 0x24003000 + + + PLLSAIM + Division factor for audio PLLSAI input + clock + 0 + 6 + + + PLLSAIN + PLLSAI division factor for + VCO + 6 + 9 + + + PLLSAIP + PLLSAI division factor for 48 MHz + clock + 16 + 2 + + + PLLSAIQ + PLLSAI division factor for SAIs + clock + 24 + 4 + + + + + DCKCFGR + DCKCFGR + Dedicated Clock Configuration + Register + 0x8C + 0x20 + read-write + 0x00000000 + + + PLLI2SDIVQ + PLLI2S division factor for SAIs + clock + 0 + 5 + + + PLLSAIDIVQ + PLLSAI division factor for SAIs + clock + 8 + 5 + + + SAI1SRC + SAI1 clock source + selection + 20 + 2 + + + SAI2SRC + SAI2 clock source + selection + 22 + 2 + + + TIMPRE + Timers clocks prescalers + selection + 24 + 1 + + + I2S1SRC + I2S APB1 clock source + selection + 25 + 2 + + + I2S2SRC + I2S APB2 clock source + selection + 27 + 2 + + + + + CKGATENR + CKGATENR + clocks gated enable register + 0x90 + 0x20 + read-write + 0x00000000 + + + AHB2APB1_CKEN + AHB to APB1 Bridge clock + enable + 0 + 1 + + + AHB2APB2_CKEN + AHB to APB2 Bridge clock + enable + 1 + 1 + + + CM4DBG_CKEN + Cortex M4 ETM clock enable + 2 + 1 + + + SPARE_CKEN + Spare clock enable + 3 + 1 + + + SRAM_CKEN + SRQAM controller clock + enable + 4 + 1 + + + FLITF_CKEN + Flash Interface clock + enable + 5 + 1 + + + RCC_CKEN + RCC clock enable + 6 + 1 + + + + + DCKCFGR2 + DCKCFGR2 + dedicated clocks configuration register + 2 + 0x94 + 0x20 + read-write + 0x00000000 + + + FMPI2C1SEL + I2C4 kernel clock source + selection + 22 + 2 + + + CECSEL + HDMI CEC clock source + selection + 26 + 1 + + + CK48MSEL + SDIO/USBFS/HS clock + selection + 27 + 1 + + + SDIOSEL + SDIO clock selection + 28 + 1 + + + SPDIFSEL + SPDIF clock selection + 29 + 1 + + + + + + + GPIOH + General-purpose I/Os + GPIO + 0x40021C00 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0x00000000 + + + MODER15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODER14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODER13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODER12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODER11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODER10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODER9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODER8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODER7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODER6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODER5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODER4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODER3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODER2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODER1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODER0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x00000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 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0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x00000000 + + + OSPEEDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEEDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEEDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEEDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEEDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEEDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEEDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEEDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEEDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEEDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEEDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEEDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEEDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEEDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEEDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEEDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x64000000 + + + PUPDR15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPDR14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPDR13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPDR12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPDR11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPDR10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPDR9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPDR8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPDR7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPDR6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPDR5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPDR4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPDR3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPDR2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPDR1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPDR0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + IDR15 + Port input data (y = + 0..15) + 15 + 1 + + + IDR14 + Port input data (y = + 0..15) + 14 + 1 + + + IDR13 + Port input data (y = + 0..15) + 13 + 1 + + + IDR12 + Port input data (y = + 0..15) + 12 + 1 + + + IDR11 + Port input data (y = + 0..15) + 11 + 1 + + + IDR10 + Port input data (y = + 0..15) + 10 + 1 + + + IDR9 + Port input data (y = + 0..15) + 9 + 1 + + + IDR8 + Port input data (y = + 0..15) + 8 + 1 + + + IDR7 + Port input data (y = + 0..15) + 7 + 1 + + + IDR6 + Port input data (y = + 0..15) + 6 + 1 + + + IDR5 + Port input data (y = + 0..15) + 5 + 1 + + + IDR4 + Port input data (y = + 0..15) + 4 + 1 + + + IDR3 + Port input data (y = + 0..15) + 3 + 1 + + + IDR2 + Port input data (y = + 0..15) + 2 + 1 + + + IDR1 + Port input data (y = + 0..15) + 1 + 1 + + + IDR0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + ODR15 + Port output data (y = + 0..15) + 15 + 1 + + + ODR14 + Port output data (y = + 0..15) + 14 + 1 + + + ODR13 + Port output data (y = + 0..15) + 13 + 1 + + + ODR12 + Port output data (y = + 0..15) + 12 + 1 + + + ODR11 + Port output data (y = + 0..15) + 11 + 1 + + + ODR10 + Port output data (y = + 0..15) + 10 + 1 + + + ODR9 + Port output data (y = + 0..15) + 9 + 1 + + + ODR8 + Port output data (y = + 0..15) + 8 + 1 + + + ODR7 + Port output data (y = + 0..15) + 7 + 1 + + + ODR6 + Port output data (y = + 0..15) + 6 + 1 + + + ODR5 + Port output data (y = + 0..15) + 5 + 1 + + + ODR4 + Port output data (y = + 0..15) + 4 + 1 + + + ODR3 + Port output data (y = + 0..15) + 3 + 1 + + + ODR2 + Port output data (y = + 0..15) + 2 + 1 + + + ODR1 + Port output data (y = + 0..15) + 1 + 1 + + + ODR0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + Port x reset bit y (y = + 0..15) + 31 + 1 + + + BR14 + Port x reset bit y (y = + 0..15) + 30 + 1 + + + BR13 + Port x reset bit y (y = + 0..15) + 29 + 1 + + + BR12 + Port x reset bit y (y = + 0..15) + 28 + 1 + + + BR11 + Port x reset bit y (y = + 0..15) + 27 + 1 + + + BR10 + Port x reset bit y (y = + 0..15) + 26 + 1 + + + BR9 + Port x reset bit y (y = + 0..15) + 25 + 1 + + + BR8 + Port x reset bit y (y = + 0..15) + 24 + 1 + + + BR7 + Port x reset bit y (y = + 0..15) + 23 + 1 + + + BR6 + Port x reset bit y (y = + 0..15) + 22 + 1 + + + BR5 + Port x reset bit y (y = + 0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS15 + Port x set bit y (y= + 0..15) + 15 + 1 + + + BS14 + Port x set bit y (y= + 0..15) + 14 + 1 + + + BS13 + Port x set bit y (y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + + LCK12 + Port x lock bit y (y= + 0..15) + 12 + 1 + + + LCK11 + Port x lock bit y (y= + 0..15) + 11 + 1 + + + LCK10 + Port x lock bit y (y= + 0..15) + 10 + 1 + + + LCK9 + Port x lock bit y (y= + 0..15) + 9 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + LCK6 + Port x lock bit y (y= + 0..15) + 6 + 1 + + + LCK5 + Port x lock bit y (y= + 0..15) + 5 + 1 + + + LCK4 + Port x lock bit y (y= + 0..15) + 4 + 1 + + + LCK3 + Port x lock bit y (y= + 0..15) + 3 + 1 + + + LCK2 + Port x lock bit y (y= + 0..15) + 2 + 1 + + + LCK1 + Port x lock bit y (y= + 0..15) + 1 + 1 + + + LCK0 + Port x lock bit y (y= + 0..15) + 0 + 1 + + + + + AFRL + AFRL + GPIO alternate function low + register + 0x20 + 0x20 + read-write + 0x00000000 + + + AFRL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFRL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFRL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFRL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFRL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFRL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFRL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFRL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFRH15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFRH14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFRH13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFRH12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFRH11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFRH10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFRH9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFRH8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40013800 + + 0x0 + 0x400 + registers + + + + MEMRM + MEMRM + memory remap register + 0x0 + 0x20 + read-write + 0x00000000 + + + MEM_MODE + Memory mapping selection + 0 + 3 + + + FB_MODE + Flash bank mode selection + 8 + 1 + + + SWP_FMC + FMC memory mapping swap + 10 + 2 + + + + + PMC + PMC + peripheral mode configuration + register + 0x4 + 0x20 + read-write + 0x00000000 + + + MII_RMII_SEL + Ethernet PHY interface + selection + 23 + 1 + + + ADC1DC2 + ADC1DC2 + 16 + 1 + + + ADC2DC2 + ADC2DC2 + 17 + 1 + + + ADC3DC2 + ADC3DC2 + 18 + 1 + + + + + EXTICR1 + EXTICR1 + external interrupt configuration register + 1 + 0x8 + 0x20 + read-write + 0x0000 + + + EXTI3 + EXTI x configuration (x = 0 to + 3) + 12 + 4 + + + EXTI2 + EXTI x configuration (x = 0 to + 3) + 8 + 4 + + + EXTI1 + EXTI x configuration (x = 0 to + 3) + 4 + 4 + + + EXTI0 + EXTI x configuration (x = 0 to + 3) + 0 + 4 + + + + + EXTICR2 + EXTICR2 + external interrupt configuration register + 2 + 0xC + 0x20 + read-write + 0x0000 + + + EXTI7 + EXTI x configuration (x = 4 to + 7) + 12 + 4 + + + EXTI6 + EXTI x configuration (x = 4 to + 7) + 8 + 4 + + + EXTI5 + EXTI x configuration (x = 4 to + 7) + 4 + 4 + + + EXTI4 + EXTI x configuration (x = 4 to + 7) + 0 + 4 + + + + + EXTICR3 + EXTICR3 + external interrupt configuration register + 3 + 0x10 + 0x20 + read-write + 0x0000 + + + EXTI11 + EXTI x configuration (x = 8 to + 11) + 12 + 4 + + + EXTI10 + EXTI10 + 8 + 4 + + + EXTI9 + EXTI x configuration (x = 8 to + 11) + 4 + 4 + + + EXTI8 + EXTI x configuration (x = 8 to + 11) + 0 + 4 + + + + + EXTICR4 + EXTICR4 + external interrupt configuration register + 4 + 0x14 + 0x20 + read-write + 0x0000 + + + EXTI15 + EXTI x configuration (x = 12 to + 15) + 12 + 4 + + + EXTI14 + EXTI x configuration (x = 12 to + 15) + 8 + 4 + + + EXTI13 + EXTI x configuration (x = 12 to + 15) + 4 + 4 + + + EXTI12 + EXTI x configuration (x = 12 to + 15) + 0 + 4 + + + + + CMPCR + CMPCR + Compensation cell control + register + 0x20 + 0x20 + read-only + 0x00000000 + + + READY + READY + 8 + 1 + + + CMP_PD + Compensation cell + power-down + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global interrupt + 35 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + CRCEN + Hardware CRC calculation + enable + 13 + 1 + + + CRCNEXT + CRC transfer next + 12 + 1 + + + DFF + Data frame format + 11 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave select + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + FRF + Frame format + 4 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + TIFRFE + TI frame format error + 8 + 1 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + CRCERR + CRC error flag + 4 + 1 + read-write + + + UDR + Underrun flag + 3 + 1 + read-only + + + CHSIDE + Channel side + 2 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + CRCPR + CRCPR + CRC polynomial register + 0x10 + 0x20 + read-write + 0x0007 + + + CRCPOLY + CRC polynomial register + 0 + 16 + + + + + RXCRCR + RXCRCR + RX CRC register + 0x14 + 0x20 + read-only + 0x0000 + + + RxCRC + Rx CRC register + 0 + 16 + + + + + TXCRCR + TXCRCR + TX CRC register + 0x18 + 0x20 + read-only + 0x0000 + + + TxCRC + Tx CRC register + 0 + 16 + + + + + I2SCFGR + I2SCFGR + I2S configuration register + 0x1C + 0x20 + read-write + 0x0000 + + + I2SMOD + I2S mode selection + 11 + 1 + + + I2SE + I2S Enable + 10 + 1 + + + I2SCFG + I2S configuration mode + 8 + 2 + + + PCMSYNC + PCM frame synchronization + 7 + 1 + + + I2SSTD + I2S standard selection + 4 + 2 + + + CKPOL + Steady state clock + polarity + 3 + 1 + + + DATLEN + Data length to be + transferred + 1 + 2 + + + CHLEN + Channel length (number of bits per audio + channel) + 0 + 1 + + + + + I2SPR + I2SPR + I2S prescaler register + 0x20 + 0x20 + read-write + 00000010 + + + MCKOE + Master clock output enable + 9 + 1 + + + ODD + Odd factor for the + prescaler + 8 + 1 + + + I2SDIV + I2S Linear prescaler + 0 + 8 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global interrupt + 36 + + + + SPI3 + 0x40003C00 + + SPI3 + SPI3 global interrupt + 51 + + + + SPI4 + 0x40013400 + + SPI4 + SPI 4 global interrupt + 84 + + + + ADC1 + Analog-to-digital converter + ADC + 0x40012000 + + 0x0 + 0x51 + registers + + + + SR + SR + status register + 0x0 + 0x20 + read-write + 0x00000000 + + + OVR + Overrun + 5 + 1 + + + STRT + Regular channel start flag + 4 + 1 + + + JSTRT + Injected channel start + flag + 3 + 1 + + + JEOC + Injected channel end of + conversion + 2 + 1 + + + EOC + Regular channel end of + conversion + 1 + 1 + + + AWD + Analog watchdog flag + 0 + 1 + + + + + CR1 + CR1 + control register 1 + 0x4 + 0x20 + read-write + 0x00000000 + + + OVRIE + Overrun interrupt enable + 26 + 1 + + + RES + Resolution + 24 + 2 + + + AWDEN + Analog watchdog enable on regular + channels + 23 + 1 + + + JAWDEN + Analog watchdog enable on injected + channels + 22 + 1 + + + DISCNUM + Discontinuous mode channel + count + 13 + 3 + + + JDISCEN + Discontinuous mode on injected + channels + 12 + 1 + + + DISCEN + Discontinuous mode on regular + channels + 11 + 1 + + + JAUTO + Automatic injected group + conversion + 10 + 1 + + + AWDSGL + Enable the watchdog on a single channel + in scan mode + 9 + 1 + + + SCAN + Scan mode + 8 + 1 + + + JEOCIE + Interrupt enable for injected + channels + 7 + 1 + + + AWDIE + Analog watchdog interrupt + enable + 6 + 1 + + + EOCIE + Interrupt enable for EOC + 5 + 1 + + + AWDCH + Analog watchdog channel select + bits + 0 + 5 + + + + + CR2 + CR2 + control register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + SWSTART + Start conversion of regular + channels + 30 + 1 + + + EXTEN + External trigger enable for regular + channels + 28 + 2 + + + EXTSEL + External event select for regular + group + 24 + 4 + + + JSWSTART + Start conversion of injected + channels + 22 + 1 + + + JEXTEN + External trigger enable for injected + channels + 20 + 2 + + + JEXTSEL + External event select for injected + group + 16 + 4 + + + ALIGN + Data alignment + 11 + 1 + + + EOCS + End of conversion + selection + 10 + 1 + + + DDS + DMA disable selection (for single ADC + mode) + 9 + 1 + + + DMA + Direct memory access mode (for single + ADC mode) + 8 + 1 + + + CONT + Continuous conversion + 1 + 1 + + + ADON + A/D Converter ON / OFF + 0 + 1 + + + + + SMPR1 + SMPR1 + sample time register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + SMPR2 + SMPR2 + sample time register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + SMPx_x + Sample time bits + 0 + 32 + + + + + JOFR1 + JOFR1 + injected channel data offset register + x + 0x14 + 0x20 + read-write + 0x00000000 + + + JOFFSET1 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR2 + JOFR2 + injected channel data offset register + x + 0x18 + 0x20 + read-write + 0x00000000 + + + JOFFSET2 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR3 + JOFR3 + injected channel data offset register + x + 0x1C + 0x20 + read-write + 0x00000000 + + + JOFFSET3 + Data offset for injected channel + x + 0 + 12 + + + + + JOFR4 + JOFR4 + injected channel data offset register + x + 0x20 + 0x20 + read-write + 0x00000000 + + + JOFFSET4 + Data offset for injected channel + x + 0 + 12 + + + + + HTR + HTR + watchdog higher threshold + register + 0x24 + 0x20 + read-write + 0x00000FFF + + + HT + Analog watchdog higher + threshold + 0 + 12 + + + + + LTR + LTR + watchdog lower threshold + register + 0x28 + 0x20 + read-write + 0x00000000 + + + LT + Analog watchdog lower + threshold + 0 + 12 + + + + + SQR1 + SQR1 + regular sequence register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + L + Regular channel sequence + length + 20 + 4 + + + SQ16 + 16th conversion in regular + sequence + 15 + 5 + + + SQ15 + 15th conversion in regular + sequence + 10 + 5 + + + SQ14 + 14th conversion in regular + sequence + 5 + 5 + + + SQ13 + 13th conversion in regular + sequence + 0 + 5 + + + + + SQR2 + SQR2 + regular sequence register 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + SQ12 + 12th conversion in regular + sequence + 25 + 5 + + + SQ11 + 11th conversion in regular + sequence + 20 + 5 + + + SQ10 + 10th conversion in regular + sequence + 15 + 5 + + + SQ9 + 9th conversion in regular + sequence + 10 + 5 + + + SQ8 + 8th conversion in regular + sequence + 5 + 5 + + + SQ7 + 7th conversion in regular + sequence + 0 + 5 + + + + + SQR3 + SQR3 + regular sequence register 3 + 0x34 + 0x20 + read-write + 0x00000000 + + + SQ6 + 6th conversion in regular + sequence + 25 + 5 + + + SQ5 + 5th conversion in regular + sequence + 20 + 5 + + + SQ4 + 4th conversion in regular + sequence + 15 + 5 + + + SQ3 + 3rd conversion in regular + sequence + 10 + 5 + + + SQ2 + 2nd conversion in regular + sequence + 5 + 5 + + + SQ1 + 1st conversion in regular + sequence + 0 + 5 + + + + + JSQR + JSQR + injected sequence register + 0x38 + 0x20 + read-write + 0x00000000 + + + JL + Injected sequence length + 20 + 2 + + + JSQ4 + 4th conversion in injected + sequence + 15 + 5 + + + JSQ3 + 3rd conversion in injected + sequence + 10 + 5 + + + JSQ2 + 2nd conversion in injected + sequence + 5 + 5 + + + JSQ1 + 1st conversion in injected + sequence + 0 + 5 + + + + + JDR1 + JDR1 + injected data register x + 0x3C + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR2 + JDR2 + injected data register x + 0x40 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR3 + JDR3 + injected data register x + 0x44 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + JDR4 + JDR4 + injected data register x + 0x48 + 0x20 + read-only + 0x00000000 + + + JDATA + Injected data + 0 + 16 + + + + + DR + DR + regular data register + 0x4C + 0x20 + read-only + 0x00000000 + + + DATA + Regular data + 0 + 16 + + + + + + + ADC2 + 0x40012100 + + + ADC3 + 0x40012200 + + + USART6 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40011400 + + 0x0 + 0x400 + registers + + + USART6 + USART6 global interrupt + 71 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + CTS + CTS flag + 9 + 1 + read-write + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + 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+ + TAMP1F + Tamper detection flag + 13 + 1 + read-write + + + TAMP2F + TAMPER2 detection flag + 14 + 1 + read-write + + + RECALPF + Recalibration pending Flag + 16 + 1 + read-only + + + + + PRER + PRER + prescaler register + 0x10 + 0x20 + read-write + 0x007F00FF + + + PREDIV_A + Asynchronous prescaler + factor + 16 + 7 + + + PREDIV_S + Synchronous prescaler + factor + 0 + 15 + + + + + WUTR + WUTR + wakeup timer register + 0x14 + 0x20 + read-write + 0x0000FFFF + + + WUT + Wakeup auto-reload value + bits + 0 + 16 + + + + + CALIBR + CALIBR + calibration register + 0x18 + 0x20 + read-write + 0x00000000 + + + DCS + Digital calibration sign + 7 + 1 + + + DC + Digital calibration + 0 + 5 + + + + + ALRMAR + ALRMAR + alarm A register + 0x1C + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm A date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm A hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm A minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm A seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + ALRMBR + ALRMBR + alarm B register + 0x20 + 0x20 + read-write + 0x00000000 + + + MSK4 + Alarm B date mask + 31 + 1 + + + WDSEL + Week day selection + 30 + 1 + + + DT + Date tens in BCD format + 28 + 2 + + + DU + Date units or day in BCD + format + 24 + 4 + + + MSK3 + Alarm B hours mask + 23 + 1 + + + PM + AM/PM notation + 22 + 1 + + + HT + Hour tens in BCD format + 20 + 2 + + + HU + Hour units in BCD format + 16 + 4 + + + MSK2 + Alarm B minutes mask + 15 + 1 + + + MNT + Minute tens in BCD format + 12 + 3 + + + MNU + Minute units in BCD format + 8 + 4 + + + MSK1 + Alarm B seconds mask + 7 + 1 + + + ST + Second tens in BCD format + 4 + 3 + + + SU + Second units in BCD format + 0 + 4 + + + + + WPR + WPR + write protection register + 0x24 + 0x20 + write-only + 0x00000000 + + + KEY + Write protection key + 0 + 8 + + + + + SSR + SSR + sub second register + 0x28 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + SHIFTR + SHIFTR + shift control register + 0x2C + 0x20 + write-only + 0x00000000 + + + ADD1S + Add one second + 31 + 1 + + + SUBFS + Subtract a fraction of a + second + 0 + 15 + + + + + TSTR + TSTR + time stamp time register + 0x30 + 0x20 + read-only + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + TSDR + TSDR + time stamp date register + 0x34 + 0x20 + read-only + 0x00000000 + + + WDU + Week day units + 13 + 3 + + + MT + Month tens in BCD format + 12 + 1 + + + MU + Month units in BCD format + 8 + 4 + + + DT + Date tens in BCD format + 4 + 2 + + + DU + Date units in BCD format + 0 + 4 + + + + + TSSSR + TSSSR + timestamp sub second register + 0x38 + 0x20 + read-only + 0x00000000 + + + SS + Sub second value + 0 + 16 + + + + + CALR + CALR + calibration register + 0x3C + 0x20 + read-write + 0x00000000 + + + CALP + Increase frequency of RTC by 488.5 + ppm + 15 + 1 + + + CALW8 + Use an 8-second calibration cycle + period + 14 + 1 + + + CALW16 + Use a 16-second calibration cycle + period + 13 + 1 + + + CALM + Calibration minus + 0 + 9 + + + + + TAFCR + TAFCR + tamper and alternate function configuration + register + 0x40 + 0x20 + read-write + 0x00000000 + + + ALARMOUTTYPE + AFO_ALARM output type + 18 + 1 + + + TSINSEL + TIMESTAMP mapping + 17 + 1 + + + TAMP1INSEL + TAMPER1 mapping + 16 + 1 + + + TAMPPUDIS + TAMPER pull-up disable + 15 + 1 + + + TAMPPRCH + Tamper precharge duration + 13 + 2 + + + TAMPFLT + Tamper filter count + 11 + 2 + + + TAMPFREQ + Tamper sampling frequency + 8 + 3 + + + TAMPTS + Activate timestamp on tamper detection + event + 7 + 1 + + + TAMP2TRG + Active level for tamper 2 + 4 + 1 + + + TAMP2E + Tamper 2 detection enable + 3 + 1 + + + TAMPIE + Tamper interrupt enable + 2 + 1 + + + TAMP1TRG + Active level for tamper 1 + 1 + 1 + + + TAMP1E + Tamper 1 detection enable + 0 + 1 + + + + + ALRMASSR + ALRMASSR + alarm A sub second register + 0x44 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + ALRMBSSR + ALRMBSSR + alarm B sub second register + 0x48 + 0x20 + read-write + 0x00000000 + + + MASKSS + Mask the most-significant bits starting + at this bit + 24 + 4 + + + SS + Sub seconds value + 0 + 15 + + + + + BKP0R + BKP0R + backup register + 0x50 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP1R + BKP1R + backup register + 0x54 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP2R + BKP2R + backup register + 0x58 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP3R + BKP3R + backup register + 0x5C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP4R + BKP4R + backup register + 0x60 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP5R + BKP5R + backup register + 0x64 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP6R + BKP6R + backup register + 0x68 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP7R + BKP7R + backup register + 0x6C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP8R + BKP8R + backup register + 0x70 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP9R + BKP9R + backup register + 0x74 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP10R + BKP10R + backup register + 0x78 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP11R + BKP11R + backup register + 0x7C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP12R + BKP12R + backup register + 0x80 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP13R + BKP13R + backup register + 0x84 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP14R + BKP14R + backup register + 0x88 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP15R + BKP15R + backup register + 0x8C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP16R + BKP16R + backup register + 0x90 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP17R + BKP17R + backup register + 0x94 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP18R + BKP18R + backup register + 0x98 + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + BKP19R + BKP19R + backup register + 0x9C + 0x20 + read-write + 0x00000000 + + + BKP + BKP + 0 + 32 + + + + + + + UART4 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40004C00 + + 0x0 + 0x400 + registers + + + UART4 + UART4 global interrupt + 52 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C00000 + + + LBD + LIN break detection flag + 8 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NF + Noise detected flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + OVER8 + Oversampling mode + 15 + 1 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + LINEN + LIN mode enable + 14 + 1 + + + STOP + STOP bits + 12 + 2 + + + LBDIE + LIN break detection interrupt + enable + 6 + 1 + + + LBDL + lin break detection length + 5 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ONEBIT + One sample bit method + enable + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + UART5 + 0x40005000 + + UART5 + UART5 global interrupt + 53 + + + + C_ADC + Common ADC registers + ADC + 0x40012300 + + 0x0 + 0xD + registers + + + ADC + ADC1 global interrupt + 18 + + + + CSR + CSR + ADC Common status register + 0x0 + 0x20 + read-only + 0x00000000 + + + OVR3 + Overrun flag of ADC3 + 21 + 1 + + + STRT3 + Regular channel Start flag of ADC + 3 + 20 + 1 + + + JSTRT3 + Injected channel Start flag of ADC + 3 + 19 + 1 + + + JEOC3 + Injected channel end of conversion of + ADC 3 + 18 + 1 + + + EOC3 + End of conversion of ADC 3 + 17 + 1 + + + AWD3 + Analog watchdog flag of ADC + 3 + 16 + 1 + + + OVR2 + Overrun flag of ADC 2 + 13 + 1 + + + STRT2 + Regular channel Start flag of ADC + 2 + 12 + 1 + + + JSTRT2 + Injected channel Start flag of ADC + 2 + 11 + 1 + + + JEOC2 + Injected channel end of conversion of + ADC 2 + 10 + 1 + + + EOC2 + End of conversion of ADC 2 + 9 + 1 + + + AWD2 + Analog watchdog flag of ADC + 2 + 8 + 1 + + + OVR1 + Overrun flag of ADC 1 + 5 + 1 + + + STRT1 + Regular channel Start flag of ADC + 1 + 4 + 1 + + + JSTRT1 + Injected channel Start flag of ADC + 1 + 3 + 1 + + + JEOC1 + Injected channel end of conversion of + ADC 1 + 2 + 1 + + + EOC1 + End of conversion of ADC 1 + 1 + 1 + + + AWD1 + Analog watchdog flag of ADC + 1 + 0 + 1 + + + + + CCR + CCR + ADC common control register + 0x4 + 0x20 + read-write + 0x00000000 + + + TSVREFE + Temperature sensor and VREFINT + enable + 23 + 1 + + + VBATE + VBAT enable + 22 + 1 + + + ADCPRE + ADC prescaler + 16 + 2 + + + DMA + Direct memory access mode for multi ADC + mode + 14 + 2 + + + DDS + DMA disable selection for multi-ADC + mode + 13 + 1 + + + DELAY + Delay between 2 sampling + phases + 8 + 4 + + + MULT + Multi ADC mode selection + 0 + 5 + + + + + CDR + CDR + ADC common regular data register for dual + and triple modes + 0x8 + 0x20 + read-only + 0x00000000 + + + DATA2 + 2nd data item of a pair of regular + conversions + 16 + 16 + + + DATA1 + 1st data item of a pair of regular + conversions + 0 + 16 + + + + + + + TIM1 + Advanced-timers + TIM + 0x40010000 + + 0x0 + 0x400 + registers + + + TIM1_BRK_TIM9 + TIM1 Break interrupt and TIM9 global + interrupt + 24 + + + TIM1_UP_TIM10 + TIM1 Update interrupt and TIM10 global + interrupt + 25 + + + TIM1_TRG_COM_TIM11 + TIM1 Trigger and Commutation interrupts and + TIM11 global interrupt + 26 + + + TIM1_CC + TIM1 Capture Compare interrupt + 27 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + COMDE + COM DMA request enable + 13 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + + + TIM8 + 0x40010400 + + TIM8_BRK_TIM12 + TIM8 Break interrupt and TIM12 global + interrupt + 43 + + + TIM8_UP_TIM13 + TIM8 Update interrupt and TIM13 global + interrupt + 44 + + + TIM8_TRG_COM_TIM14 + TIM8 Trigger and Commutation interrupts and + TIM14 global interrupt + 45 + + + TIM8_CC + TIM8 Capture Compare interrupt + 46 + + + + TIM2 + General purpose timers + TIM + 0x40000000 + + 0x0 + 0x400 + registers + + + TIM2 + TIM2 global interrupt + 28 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TDE + Trigger DMA request enable + 14 + 1 + + + CC4DE + Capture/Compare 4 DMA request + enable + 12 + 1 + + + CC3DE + Capture/Compare 3 DMA request + enable + 11 + 1 + + + CC2DE + Capture/Compare 2 DMA request + enable + 10 + 1 + + + CC1DE + Capture/Compare 1 DMA request + enable + 9 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Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + TIE + Trigger interrupt enable + 6 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + TG + Trigger generation + 6 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 3 + + + IC2PCS + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 3 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + + + TIM12 + 0x40001800 + + + TIM10 + General-purpose-timers + TIM + 0x40014400 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + + + TIM13 + 0x40001C00 + + + TIM14 + 0x40002000 + + + TIM11 + General-purpose-timers + TIM + 0x40014800 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPCS + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + OR + OR + option register + 0x50 + 0x20 + read-write + 0x00000000 + + + RMP + Input 1 remapping + capability + 0 + 2 + + + + + + + TIM6 + Basic timers + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_DAC + TIM6 global interrupt, DAC1 and DAC2 underrun + error interrupt + 54 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + MMS + Master mode selection + 4 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UDE + Update DMA request enable + 8 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + Low counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Low Auto-reload value + 0 + 16 + + + + + + + TIM7 + 0x40001400 + + TIM7 + TIM7 global interrupt + 55 + + + + CRC + Cryptographic processor + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + CR + Control regidter + 0 + 1 + + + + + + + OTG_FS_GLOBAL + USB on the go full speed + USB_OTG_FS + 0x50000000 + + 0x0 + 0x400 + registers + + + OTG_FS_WKUP + USB On-The-Go FS Wakeup through EXTI line + interrupt + 42 + + + OTG_FS + USB On The Go FS global + interrupt + 67 + + + + FS_GOTGCTL + FS_GOTGCTL + OTG_FS control and status register + (OTG_FS_GOTGCTL) + 0x0 + 0x20 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + FS_GOTGINT + FS_GOTGINT + OTG_FS interrupt register + (OTG_FS_GOTGINT) + 0x4 + 0x20 + read-write + 0x00000000 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + FS_GAHBCFG + FS_GAHBCFG + OTG_FS AHB configuration register + (OTG_FS_GAHBCFG) + 0x8 + 0x20 + read-write + 0x00000000 + + + GINT + Global interrupt mask + 0 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + FS_GUSBCFG + FS_GUSBCFG + OTG_FS USB configuration register + (OTG_FS_GUSBCFG) + 0xC + 0x20 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + Full Speed serial transceiver + select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + FHMOD + Force host mode + 29 + 1 + read-write + + + FDMOD + Force device mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + FS_GRSTCTL + FS_GRSTCTL + OTG_FS reset register + (OTG_FS_GRSTCTL) + 0x10 + 0x20 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + FS_GINTSTS + FS_GINTSTS + OTG_FS core interrupt register + (OTG_FS_GINTSTS) + 0x14 + 0x20 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO non-empty + 4 + 1 + read-only + + + NPTXFE + Non-periodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN non-periodic NAK + effective + 6 + 1 + read-only + + + GOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + IPXFR_INCOMPISOOUT + Incomplete periodic transfer(Host + mode)/Incomplete isochronous OUT transfer(Device + mode) + 21 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUPINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + FS_GINTMSK + FS_GINTMSK + OTG_FS interrupt mask register + (OTG_FS_GINTMSK) + 0x18 + 0x20 + 0x00000000 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO non-empty + mask + 4 + 1 + read-write + + + NPTXFEM + Non-periodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global non-periodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + IPXFRM_IISOOXFRM + Incomplete periodic transfer mask(Host + mode)/Incomplete isochronous OUT transfer mask(Device + mode) + 21 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + FS_GRXSTSR_Device + FS_GRXSTSR_Device + OTG_FS Receive status debug read(Device + mode) + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXSTSR_Host + FS_GRXSTSR_Host + OTG_FS Receive status debug read(Host + mode) + FS_GRXSTSR_Device + 0x1C + 0x20 + read-only + 0x00000000 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + FS_GRXFSIZ + FS_GRXFSIZ + OTG_FS Receive FIFO size register + (OTG_FS_GRXFSIZ) + 0x24 + 0x20 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + FS_GNPTXFSIZ_Device + FS_GNPTXFSIZ_Device + OTG_FS non-periodic transmit FIFO size + register (Device mode) + 0x28 + 0x20 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + FS_GNPTXFSIZ_Host + FS_GNPTXFSIZ_Host + OTG_FS non-periodic transmit FIFO size + register (Host mode) + FS_GNPTXFSIZ_Device + 0x28 + 0x20 + read-write + 0x00000200 + + + NPTXFSA + Non-periodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Non-periodic TxFIFO depth + 16 + 16 + + + + + FS_GNPTXSTS + FS_GNPTXSTS + OTG_FS non-periodic transmit FIFO/queue + status register (OTG_FS_GNPTXSTS) + 0x2C + 0x20 + read-only + 0x00080200 + + + NPTXFSAV + Non-periodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Non-periodic transmit request queue + space available + 16 + 8 + + + NPTXQTOP + Top of the non-periodic transmit request + queue + 24 + 7 + + + + + FS_GCCFG + FS_GCCFG + OTG_FS general core configuration register + (OTG_FS_GCCFG) + 0x38 + 0x20 + read-write + 0x00000000 + + + PWRDWN + Power down + 16 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + + + FS_CID + FS_CID + core ID register + 0x3C + 0x20 + read-write + 0x00001000 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + FS_HPTXFSIZ + FS_HPTXFSIZ + OTG_FS Host periodic transmit FIFO size + register (OTG_FS_HPTXFSIZ) + 0x100 + 0x20 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFSIZ + Host periodic TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF1 + FS_DIEPTXF1 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF2) + 0x104 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO2 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF2 + FS_DIEPTXF2 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF3) + 0x108 + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO3 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + FS_DIEPTXF3 + FS_DIEPTXF3 + OTG_FS device IN endpoint transmit FIFO size + register (OTG_FS_DIEPTXF4) + 0x10C + 0x20 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFO4 transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + + + OTG_FS_HOST + USB on the go full speed + USB_OTG_FS + 0x50000400 + + 0x0 + 0x400 + registers + + + + FS_HCFG + FS_HCFG + OTG_FS host configuration register + (OTG_FS_HCFG) + 0x0 + 0x20 + 0x00000000 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + HFIR + HFIR + OTG_FS Host frame interval + register + 0x4 + 0x20 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + + + FS_HFNUM + FS_HFNUM + OTG_FS host frame number/frame time + remaining register (OTG_FS_HFNUM) + 0x8 + 0x20 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + FS_HPTXSTS + FS_HPTXSTS + OTG_FS_Host periodic transmit FIFO/queue + status register (OTG_FS_HPTXSTS) + 0x10 + 0x20 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + HAINT + HAINT + OTG_FS Host all channels interrupt + register + 0x14 + 0x20 + read-only + 0x00000000 + + + HAINT + Channel interrupts + 0 + 16 + + + + + HAINTMSK + HAINTMSK + OTG_FS host all channels interrupt mask + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + FS_HPRT + FS_HPRT + OTG_FS host port control and status register + (OTG_FS_HPRT) + 0x40 + 0x20 + 0x00000000 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + FS_HCCHAR0 + FS_HCCHAR0 + OTG_FS host channel-0 characteristics + register (OTG_FS_HCCHAR0) + 0x100 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR1 + FS_HCCHAR1 + OTG_FS host channel-1 characteristics + register (OTG_FS_HCCHAR1) + 0x120 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR2 + FS_HCCHAR2 + OTG_FS host channel-2 characteristics + register (OTG_FS_HCCHAR2) + 0x140 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR3 + FS_HCCHAR3 + OTG_FS host channel-3 characteristics + register (OTG_FS_HCCHAR3) + 0x160 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR4 + FS_HCCHAR4 + OTG_FS host channel-4 characteristics + register (OTG_FS_HCCHAR4) + 0x180 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR5 + FS_HCCHAR5 + OTG_FS host channel-5 characteristics + register (OTG_FS_HCCHAR5) + 0x1A0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR6 + FS_HCCHAR6 + OTG_FS host channel-6 characteristics + register (OTG_FS_HCCHAR6) + 0x1C0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR7 + FS_HCCHAR7 + OTG_FS host channel-7 characteristics + register (OTG_FS_HCCHAR7) + 0x1E0 + 0x20 + read-write + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multicount + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR8 + FS_HCCHAR8 + OTG_FS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR9 + FS_HCCHAR9 + OTG_FS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR10 + FS_HCCHAR10 + OTG_FS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCCHAR11 + FS_HCCHAR11 + OTG_FS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + FS_HCINT0 + FS_HCINT0 + OTG_FS host channel-0 interrupt register + (OTG_FS_HCINT0) + 0x108 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT1 + FS_HCINT1 + OTG_FS host channel-1 interrupt register + (OTG_FS_HCINT1) + 0x128 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT2 + FS_HCINT2 + OTG_FS host channel-2 interrupt register + (OTG_FS_HCINT2) + 0x148 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT3 + FS_HCINT3 + OTG_FS host channel-3 interrupt register + (OTG_FS_HCINT3) + 0x168 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT4 + FS_HCINT4 + OTG_FS host channel-4 interrupt register + (OTG_FS_HCINT4) + 0x188 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT5 + FS_HCINT5 + OTG_FS host channel-5 interrupt register + (OTG_FS_HCINT5) + 0x1A8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT6 + FS_HCINT6 + OTG_FS host channel-6 interrupt register + (OTG_FS_HCINT6) + 0x1C8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT7 + FS_HCINT7 + OTG_FS host channel-7 interrupt register + (OTG_FS_HCINT7) + 0x1E8 + 0x20 + read-write + 0x00000000 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT8 + FS_HCINT8 + OTG_FS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT9 + FS_HCINT9 + OTG_FS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT10 + FS_HCINT10 + OTG_FS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINT11 + FS_HCINT11 + OTG_FS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + FS_HCINTMSK0 + FS_HCINTMSK0 + OTG_FS host channel-0 mask register + (OTG_FS_HCINTMSK0) + 0x10C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK1 + FS_HCINTMSK1 + OTG_FS host channel-1 mask register + (OTG_FS_HCINTMSK1) + 0x12C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK2 + FS_HCINTMSK2 + OTG_FS host channel-2 mask register + (OTG_FS_HCINTMSK2) + 0x14C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK3 + FS_HCINTMSK3 + OTG_FS host channel-3 mask register + (OTG_FS_HCINTMSK3) + 0x16C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK4 + FS_HCINTMSK4 + OTG_FS host channel-4 mask register + (OTG_FS_HCINTMSK4) + 0x18C + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK5 + FS_HCINTMSK5 + OTG_FS host channel-5 mask register + (OTG_FS_HCINTMSK5) + 0x1AC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK6 + FS_HCINTMSK6 + OTG_FS host channel-6 mask register + (OTG_FS_HCINTMSK6) + 0x1CC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK7 + FS_HCINTMSK7 + OTG_FS host channel-7 mask register + (OTG_FS_HCINTMSK7) + 0x1EC + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK8 + FS_HCINTMSK8 + OTG_FS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK9 + FS_HCINTMSK9 + OTG_FS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK10 + FS_HCINTMSK10 + OTG_FS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCINTMSK11 + FS_HCINTMSK11 + OTG_FS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + FS_HCTSIZ0 + FS_HCTSIZ0 + OTG_FS host channel-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ1 + FS_HCTSIZ1 + OTG_FS host channel-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ2 + FS_HCTSIZ2 + OTG_FS host channel-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ3 + FS_HCTSIZ3 + OTG_FS host channel-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ4 + FS_HCTSIZ4 + OTG_FS host channel-x transfer size + register + 0x190 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ5 + FS_HCTSIZ5 + OTG_FS host channel-5 transfer size + register + 0x1B0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ6 + FS_HCTSIZ6 + OTG_FS host channel-6 transfer size + register + 0x1D0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ7 + FS_HCTSIZ7 + OTG_FS host channel-7 transfer size + register + 0x1F0 + 0x20 + read-write + 0x00000000 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ8 + FS_HCTSIZ8 + OTG_FS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ9 + FS_HCTSIZ9 + OTG_FS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ10 + FS_HCTSIZ10 + OTG_FS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + FS_HCTSIZ11 + FS_HCTSIZ11 + OTG_FS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + + + OTG_FS_DEVICE + USB on the go full speed + USB_OTG_FS + 0x50000800 + + 0x0 + 0x400 + registers + + + + FS_DCFG + FS_DCFG + OTG_FS device configuration register + (OTG_FS_DCFG) + 0x0 + 0x20 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Non-zero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic frame interval + 11 + 2 + + + ERRATIM + Erratic error interrupt + mask + 15 + 1 + + + + + FS_DCTL + FS_DCTL + OTG_FS device control register + (OTG_FS_DCTL) + 0x4 + 0x20 + 0x00000000 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + read-write + + + CGINAK + Clear global IN NAK + 8 + 1 + read-write + + + SGONAK + Set global OUT NAK + 9 + 1 + read-write + + + CGONAK + Clear global OUT NAK + 10 + 1 + read-write + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + FS_DSTS + FS_DSTS + OTG_FS device status register + (OTG_FS_DSTS) + 0x8 + 0x20 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + FS_DIEPMSK + FS_DIEPMSK + OTG_FS device IN endpoint common interrupt + mask register (OTG_FS_DIEPMSK) + 0x10 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (Non-isochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + + + FS_DOEPMSK + FS_DOEPMSK + OTG_FS device OUT endpoint common interrupt + mask register (OTG_FS_DOEPMSK) + 0x14 + 0x20 + read-write + 0x00000000 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + + + FS_DAINT + FS_DAINT + OTG_FS device all endpoints interrupt + register (OTG_FS_DAINT) + 0x18 + 0x20 + read-only + 0x00000000 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + FS_DAINTMSK + FS_DAINTMSK + OTG_FS all endpoints interrupt mask register + (OTG_FS_DAINTMSK) + 0x1C + 0x20 + read-write + 0x00000000 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + DVBUSDIS + DVBUSDIS + OTG_FS device VBUS discharge time + register + 0x28 + 0x20 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + DVBUSPULSE + DVBUSPULSE + OTG_FS device VBUS pulsing time + register + 0x2C + 0x20 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + DIEPEMPMSK + DIEPEMPMSK + OTG_FS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 0x20 + read-write + 0x00000000 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + FS_DIEPCTL0 + FS_DIEPCTL0 + OTG_FS device control IN endpoint 0 control + register (OTG_FS_DIEPCTL0) + 0x100 + 0x20 + 0x00000000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + STALL + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + read-only + + + + + DIEPCTL1 + DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM_SD1PID + SODDFRM/SD1PID + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL2 + DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPCTL3 + DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + TXFNUM + TXFNUM + 22 + 4 + read-write + + + Stall + Stall + 21 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL0 + DOEPCTL0 + device endpoint-0 control + register + 0x300 + 0x20 + 0x00008000 + + + EPENA + EPENA + 31 + 1 + write-only + + + EPDIS + EPDIS + 30 + 1 + read-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-only + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-only + + + MPSIZ + MPSIZ + 0 + 2 + read-only + + + + + DOEPCTL1 + DOEPCTL1 + device endpoint-1 control + register + 0x320 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL2 + DOEPCTL2 + device endpoint-2 control + register + 0x340 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DOEPCTL3 + DOEPCTL3 + device endpoint-3 control + register + 0x360 + 0x20 + 0x00000000 + + + EPENA + EPENA + 31 + 1 + read-write + + + EPDIS + EPDIS + 30 + 1 + read-write + + + SODDFRM + SODDFRM + 29 + 1 + write-only + + + SD0PID_SEVNFRM + SD0PID/SEVNFRM + 28 + 1 + write-only + + + SNAK + SNAK + 27 + 1 + write-only + + + CNAK + CNAK + 26 + 1 + write-only + + + Stall + Stall + 21 + 1 + read-write + + + SNPM + SNPM + 20 + 1 + read-write + + + EPTYP + EPTYP + 18 + 2 + read-write + + + NAKSTS + NAKSTS + 17 + 1 + read-only + + + EONUM_DPID + EONUM/DPID + 16 + 1 + read-only + + + USBAEP + USBAEP + 15 + 1 + read-write + + + MPSIZ + MPSIZ + 0 + 11 + read-write + + + + + DIEPINT0 + DIEPINT0 + device endpoint-x interrupt + register + 0x108 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT1 + DIEPINT1 + device endpoint-1 interrupt + register + 0x128 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT2 + DIEPINT2 + device endpoint-2 interrupt + register + 0x148 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DIEPINT3 + DIEPINT3 + device endpoint-3 interrupt + register + 0x168 + 0x20 + 0x00000080 + + + TXFE + TXFE + 7 + 1 + read-only + + + INEPNE + INEPNE + 6 + 1 + read-write + + + ITTXFE + ITTXFE + 4 + 1 + read-write + + + TOC + TOC + 3 + 1 + read-write + + + EPDISD + EPDISD + 1 + 1 + read-write + + + XFRC + XFRC + 0 + 1 + read-write + + + + + DOEPINT0 + DOEPINT0 + device endpoint-0 interrupt + register + 0x308 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT1 + DOEPINT1 + device endpoint-1 interrupt + register + 0x328 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT2 + DOEPINT2 + device endpoint-2 interrupt + register + 0x348 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DOEPINT3 + DOEPINT3 + device endpoint-3 interrupt + register + 0x368 + 0x20 + read-write + 0x00000080 + + + B2BSTUP + B2BSTUP + 6 + 1 + + + OTEPDIS + OTEPDIS + 4 + 1 + + + STUP + STUP + 3 + 1 + + + EPDISD + EPDISD + 1 + 1 + + + XFRC + XFRC + 0 + 1 + + + + + DIEPTSIZ0 + DIEPTSIZ0 + device endpoint-0 transfer size + register + 0x110 + 0x20 + read-write + 0x00000000 + + + PKTCNT + Packet count + 19 + 2 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DOEPTSIZ0 + DOEPTSIZ0 + device OUT endpoint-0 transfer size + register + 0x310 + 0x20 + read-write + 0x00000000 + + + STUPCNT + SETUP packet count + 29 + 2 + + + PKTCNT + Packet count + 19 + 1 + + + XFRSIZ + Transfer size + 0 + 7 + + + + + DIEPTSIZ1 + DIEPTSIZ1 + device endpoint-1 transfer size + register + 0x130 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ2 + DIEPTSIZ2 + device endpoint-2 transfer size + register + 0x150 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DIEPTSIZ3 + DIEPTSIZ3 + device endpoint-3 transfer size + register + 0x170 + 0x20 + read-write + 0x00000000 + + + MCNT + Multi count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DTXFSTS0 + DTXFSTS0 + OTG_FS device IN endpoint transmit FIFO + status register + 0x118 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS1 + DTXFSTS1 + OTG_FS device IN endpoint transmit FIFO + status register + 0x138 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS2 + DTXFSTS2 + OTG_FS device IN endpoint transmit FIFO + status register + 0x158 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DTXFSTS3 + DTXFSTS3 + OTG_FS device IN endpoint transmit FIFO + status register + 0x178 + 0x20 + read-only + 0x00000000 + + + INEPTFSAV + IN endpoint TxFIFO space + available + 0 + 16 + + + + + DOEPTSIZ1 + DOEPTSIZ1 + device OUT endpoint-1 transfer size + register + 0x330 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ2 + DOEPTSIZ2 + device OUT endpoint-2 transfer size + register + 0x350 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + DOEPTSIZ3 + DOEPTSIZ3 + device OUT endpoint-3 transfer size + register + 0x370 + 0x20 + read-write + 0x00000000 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + PKTCNT + Packet count + 19 + 10 + + + XFRSIZ + Transfer size + 0 + 19 + + + + + + + OTG_FS_PWRCLK + USB on the go full speed + USB_OTG_FS + 0x50000E00 + + 0x0 + 0x400 + registers + + + + FS_PCGCCTL + FS_PCGCCTL + OTG_FS power and clock gating control + register (OTG_FS_PCGCCTL) + 0x0 + 0x20 + read-write + 0x00000000 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY Suspended + 4 + 1 + + + + + + + CAN1 + Controller area network + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN1_TX + CAN1 TX interrupts + 19 + + + CAN1_RX0 + CAN1 RX0 interrupts + 20 + + + CAN1_RX1 + CAN1 RX1 interrupts + 21 + + + CAN1_SCE + CAN1 SCE interrupt + 22 + + + + MCR + MCR + master control register + 0x0 + 0x20 + read-write + 0x00010002 + + + DBF + DBF + 16 + 1 + + + RESET + RESET + 15 + 1 + + + TTCM + TTCM + 7 + 1 + + + ABOM + ABOM + 6 + 1 + + + AWUM + AWUM + 5 + 1 + + + NART + NART + 4 + 1 + + + RFLM + RFLM + 3 + 1 + + + TXFP + TXFP + 2 + 1 + + + SLEEP + SLEEP + 1 + 1 + + + INRQ + INRQ + 0 + 1 + + + + + MSR + MSR + master status register + 0x4 + 0x20 + 0x00000C02 + + + RX + RX + 11 + 1 + read-only + + + SAMP + SAMP + 10 + 1 + read-only + + + RXM + RXM + 9 + 1 + read-only + + + TXM + TXM + 8 + 1 + read-only + + + SLAKI + SLAKI + 4 + 1 + read-write + + + WKUI + WKUI + 3 + 1 + read-write + + + ERRI + ERRI + 2 + 1 + read-write + + + SLAK + SLAK + 1 + 1 + read-only + + + INAK + INAK + 0 + 1 + read-only + + + + + TSR + TSR + transmit status register + 0x8 + 0x20 + 0x1C000000 + + + LOW2 + Lowest priority flag for mailbox + 2 + 31 + 1 + read-only + + + LOW1 + Lowest priority flag for mailbox + 1 + 30 + 1 + read-only + + + LOW0 + Lowest priority flag for mailbox + 0 + 29 + 1 + read-only + + + TME2 + Lowest priority flag for mailbox + 2 + 28 + 1 + read-only + + + TME1 + Lowest priority flag for mailbox + 1 + 27 + 1 + read-only + + + TME0 + Lowest priority flag for mailbox + 0 + 26 + 1 + read-only + + + CODE + CODE + 24 + 2 + read-only + + + ABRQ2 + ABRQ2 + 23 + 1 + read-write + + + TERR2 + TERR2 + 19 + 1 + read-write + + + ALST2 + ALST2 + 18 + 1 + read-write + + + TXOK2 + TXOK2 + 17 + 1 + read-write + + + RQCP2 + RQCP2 + 16 + 1 + read-write + + + ABRQ1 + ABRQ1 + 15 + 1 + read-write + + + TERR1 + TERR1 + 11 + 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+ 1 + read-write + + + ICEN + Instruction cache enable + 9 + 1 + read-write + + + DCEN + Data cache enable + 10 + 1 + read-write + + + ICRST + Instruction cache reset + 11 + 1 + write-only + + + DCRST + Data cache reset + 12 + 1 + read-write + + + + + KEYR + KEYR + Flash key register + 0x4 + 0x20 + write-only + 0x00000000 + + + KEY + FPEC key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Flash option key register + 0x8 + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0xC + 0x20 + 0x00000000 + + + EOP + End of operation + 0 + 1 + read-write + + + OPERR + Operation error + 1 + 1 + read-write + + + WRPERR + Write protection error + 4 + 1 + read-write + + + PGAERR + Programming alignment + error + 5 + 1 + read-write + + + PGPERR + Programming parallelism + error + 6 + 1 + read-write + + + PGSERR + Programming sequence error + 7 + 1 + read-write + + + RDERR + Read Protection Error + 8 + 1 + read-write + + + BSY + Busy + 16 + 1 + read-only + + + + + CR + CR + Control register + 0x10 + 0x20 + read-write + 0x80000000 + + + PG + Programming + 0 + 1 + + + SER + Sector Erase + 1 + 1 + + + MER + Mass Erase of sectors 0 to + 11 + 2 + 1 + + + SNB + Sector number + 3 + 4 + + + PSIZE + Program size + 8 + 2 + + + STRT + Start + 16 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + LOCK + Lock + 31 + 1 + + + + + OPTCR + OPTCR + Flash option control register + 0x14 + 0x20 + read-write + 0x0FFFAAED + + + OPTLOCK + Option lock + 0 + 1 + + + OPTSTRT + Option start + 1 + 1 + + + BOR_LEV + BOR reset Level + 2 + 2 + + + WDG_SW + WDG_SW User option bytes + 5 + 1 + + + nRST_STOP + nRST_STOP User option + bytes + 6 + 1 + + + nRST_STDBY + nRST_STDBY User option + bytes + 7 + 1 + + + RDP + Read protect + 8 + 8 + + + nWRP + Not write protect + 16 + 8 + + + SPRMOD + Selection of Protection Mode of nWPRi + bits + 31 + 1 + + + + + + + EXTI + External interrupt/event + controller + EXTI + 0x40013C00 + + 0x0 + 0x400 + registers + + + PVD + PVD through EXTI line detection + interrupt + 1 + + + TAMP_STAMP + Tamper and TimeStamp interrupts through the + EXTI line + 2 + + + EXTI0 + EXTI Line0 interrupt + 6 + + + EXTI1 + EXTI Line1 interrupt + 7 + + + EXTI2 + EXTI Line2 interrupt + 8 + + + EXTI3 + EXTI Line3 interrupt + 9 + + + EXTI4 + EXTI Line4 interrupt + 10 + + + EXTI9_5 + EXTI Line[9:5] interrupts + 23 + + + EXTI15_10 + EXTI Line[15:10] interrupts + 40 + + + + IMR + IMR + Interrupt mask register + (EXTI_IMR) + 0x0 + 0x20 + read-write + 0x00000000 + + + MR0 + Interrupt Mask on line 0 + 0 + 1 + + + MR1 + Interrupt Mask on line 1 + 1 + 1 + + + MR2 + Interrupt Mask on line 2 + 2 + 1 + + + MR3 + Interrupt Mask on line 3 + 3 + 1 + + + MR4 + Interrupt Mask on line 4 + 4 + 1 + + + MR5 + Interrupt Mask on line 5 + 5 + 1 + + + MR6 + Interrupt Mask on line 6 + 6 + 1 + + + MR7 + Interrupt Mask on line 7 + 7 + 1 + + + MR8 + Interrupt Mask on line 8 + 8 + 1 + + + MR9 + Interrupt Mask on line 9 + 9 + 1 + + + MR10 + Interrupt Mask on line 10 + 10 + 1 + + + MR11 + Interrupt Mask on line 11 + 11 + 1 + + + MR12 + Interrupt Mask on line 12 + 12 + 1 + + + MR13 + Interrupt Mask on line 13 + 13 + 1 + + + MR14 + Interrupt Mask on line 14 + 14 + 1 + + + MR15 + Interrupt Mask on line 15 + 15 + 1 + + + MR16 + Interrupt Mask on line 16 + 16 + 1 + + + MR17 + Interrupt Mask on line 17 + 17 + 1 + + + MR18 + Interrupt Mask on line 18 + 18 + 1 + + + MR19 + Interrupt Mask on line 19 + 19 + 1 + + + MR20 + Interrupt Mask on line 20 + 20 + 1 + + + MR21 + Interrupt Mask on line 21 + 21 + 1 + + + MR22 + Interrupt Mask on line 22 + 22 + 1 + + + + + EMR + EMR + Event mask register (EXTI_EMR) + 0x4 + 0x20 + read-write + 0x00000000 + + + MR0 + Event Mask on line 0 + 0 + 1 + + + MR1 + Event Mask on line 1 + 1 + 1 + + + MR2 + Event Mask on line 2 + 2 + 1 + + + MR3 + Event Mask on line 3 + 3 + 1 + + + MR4 + Event Mask on line 4 + 4 + 1 + + + MR5 + Event Mask on line 5 + 5 + 1 + + + MR6 + Event Mask on line 6 + 6 + 1 + + + MR7 + Event Mask on line 7 + 7 + 1 + + + MR8 + Event Mask on line 8 + 8 + 1 + + + MR9 + Event Mask on line 9 + 9 + 1 + + + MR10 + Event Mask on line 10 + 10 + 1 + + + MR11 + Event Mask on line 11 + 11 + 1 + + + MR12 + Event Mask on line 12 + 12 + 1 + + + MR13 + Event Mask on line 13 + 13 + 1 + + + MR14 + Event Mask on line 14 + 14 + 1 + + + MR15 + Event Mask on line 15 + 15 + 1 + + + MR16 + Event Mask on line 16 + 16 + 1 + + + MR17 + Event Mask on line 17 + 17 + 1 + + + MR18 + Event Mask on line 18 + 18 + 1 + + + MR19 + Event Mask on line 19 + 19 + 1 + + + MR20 + Event Mask on line 20 + 20 + 1 + + + MR21 + Event Mask on line 21 + 21 + 1 + + + MR22 + Event Mask on line 22 + 22 + 1 + + + + + RTSR + RTSR + Rising Trigger selection register + (EXTI_RTSR) + 0x8 + 0x20 + read-write + 0x00000000 + + + TR0 + Rising trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Rising trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Rising trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Rising trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Rising trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Rising trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Rising trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Rising trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Rising trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Rising trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Rising trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Rising trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Rising trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Rising trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Rising trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Rising trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Rising trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Rising trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Rising trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Rising trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Rising trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Rising trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Rising trigger event configuration of + line 22 + 22 + 1 + + + + + FTSR + FTSR + Falling Trigger selection register + (EXTI_FTSR) + 0xC + 0x20 + read-write + 0x00000000 + + + TR0 + Falling trigger event configuration of + line 0 + 0 + 1 + + + TR1 + Falling trigger event configuration of + line 1 + 1 + 1 + + + TR2 + Falling trigger event configuration of + line 2 + 2 + 1 + + + TR3 + Falling trigger event configuration of + line 3 + 3 + 1 + + + TR4 + Falling trigger event configuration of + line 4 + 4 + 1 + + + TR5 + Falling trigger event configuration of + line 5 + 5 + 1 + + + TR6 + Falling trigger event configuration of + line 6 + 6 + 1 + + + TR7 + Falling trigger event configuration of + line 7 + 7 + 1 + + + TR8 + Falling trigger event configuration of + line 8 + 8 + 1 + + + TR9 + Falling trigger event configuration of + line 9 + 9 + 1 + + + TR10 + Falling trigger event configuration of + line 10 + 10 + 1 + + + TR11 + Falling trigger event configuration of + line 11 + 11 + 1 + + + TR12 + Falling trigger event configuration of + line 12 + 12 + 1 + + + TR13 + Falling trigger event configuration of + line 13 + 13 + 1 + + + TR14 + Falling trigger event configuration of + line 14 + 14 + 1 + + + TR15 + Falling trigger event configuration of + line 15 + 15 + 1 + + + TR16 + Falling trigger event configuration of + line 16 + 16 + 1 + + + TR17 + Falling trigger event configuration of + line 17 + 17 + 1 + + + TR18 + Falling trigger event configuration of + line 18 + 18 + 1 + + + TR19 + Falling trigger event configuration of + line 19 + 19 + 1 + + + TR20 + Falling trigger event configuration of + line 20 + 20 + 1 + + + TR21 + Falling trigger event configuration of + line 21 + 21 + 1 + + + TR22 + Falling trigger event configuration of + line 22 + 22 + 1 + + + + + SWIER + SWIER + Software interrupt event register + (EXTI_SWIER) + 0x10 + 0x20 + read-write + 0x00000000 + + + SWIER0 + Software Interrupt on line + 0 + 0 + 1 + + + SWIER1 + Software Interrupt on line + 1 + 1 + 1 + + + SWIER2 + Software Interrupt on line + 2 + 2 + 1 + + + SWIER3 + Software Interrupt on line + 3 + 3 + 1 + + + SWIER4 + Software Interrupt on line + 4 + 4 + 1 + + + SWIER5 + Software Interrupt on line + 5 + 5 + 1 + + + SWIER6 + Software Interrupt on line + 6 + 6 + 1 + + + SWIER7 + Software Interrupt on line + 7 + 7 + 1 + + + SWIER8 + Software Interrupt on line + 8 + 8 + 1 + + + SWIER9 + Software Interrupt on line + 9 + 9 + 1 + + + SWIER10 + Software Interrupt on line + 10 + 10 + 1 + + + SWIER11 + Software Interrupt on line + 11 + 11 + 1 + + + SWIER12 + Software Interrupt on line + 12 + 12 + 1 + + + SWIER13 + Software Interrupt on line + 13 + 13 + 1 + + + SWIER14 + Software Interrupt on line + 14 + 14 + 1 + + + SWIER15 + Software Interrupt on line + 15 + 15 + 1 + + + SWIER16 + Software Interrupt on line + 16 + 16 + 1 + + + SWIER17 + Software Interrupt on line + 17 + 17 + 1 + + + SWIER18 + Software Interrupt on line + 18 + 18 + 1 + + + SWIER19 + Software Interrupt on line + 19 + 19 + 1 + + + SWIER20 + Software Interrupt on line + 20 + 20 + 1 + + + SWIER21 + Software Interrupt on line + 21 + 21 + 1 + + + SWIER22 + Software Interrupt on line + 22 + 22 + 1 + + + + + PR + PR + Pending register (EXTI_PR) + 0x14 + 0x20 + read-write + 0x00000000 + + + PR0 + Pending bit 0 + 0 + 1 + + + PR1 + Pending bit 1 + 1 + 1 + + + PR2 + Pending bit 2 + 2 + 1 + + + PR3 + Pending bit 3 + 3 + 1 + + + PR4 + Pending bit 4 + 4 + 1 + + + PR5 + Pending bit 5 + 5 + 1 + + + PR6 + Pending bit 6 + 6 + 1 + + + PR7 + Pending bit 7 + 7 + 1 + + + PR8 + Pending bit 8 + 8 + 1 + + + PR9 + Pending bit 9 + 9 + 1 + + + PR10 + Pending bit 10 + 10 + 1 + + + PR11 + Pending bit 11 + 11 + 1 + + + PR12 + Pending bit 12 + 12 + 1 + + + PR13 + Pending bit 13 + 13 + 1 + + + PR14 + Pending bit 14 + 14 + 1 + + + PR15 + Pending bit 15 + 15 + 1 + + + PR16 + Pending bit 16 + 16 + 1 + + + PR17 + Pending bit 17 + 17 + 1 + + + PR18 + Pending bit 18 + 18 + 1 + + + PR19 + Pending bit 19 + 19 + 1 + + + PR20 + Pending bit 20 + 20 + 1 + + + PR21 + Pending bit 21 + 21 + 1 + + + PR22 + Pending bit 22 + 22 + 1 + + + + + + + OTG_HS_GLOBAL + USB on the go high speed + USB_OTG_HS + 0x40040000 + + 0x0 + 0x400 + registers + + + OTG_HS_EP1_OUT + USB On The Go HS End Point 1 Out + 74 + + + OTG_HS_EP1_IN + USB On The Go HS End Point 1 In + 75 + + + OTG_HS + USB On The Go HS global + interrupt + 77 + + + + OTG_HS_GOTGCTL + OTG_HS_GOTGCTL + OTG_HS control and status + register + 0x0 + 32 + 0x00000800 + + + SRQSCS + Session request success + 0 + 1 + read-only + + + SRQ + Session request + 1 + 1 + read-write + + + HNGSCS + Host negotiation success + 8 + 1 + read-only + + + HNPRQ + HNP request + 9 + 1 + read-write + + + HSHNPEN + Host set HNP enable + 10 + 1 + read-write + + + DHNPEN + Device HNP enabled + 11 + 1 + read-write + + + CIDSTS + Connector ID status + 16 + 1 + read-only + + + DBCT + Long/short debounce time + 17 + 1 + read-only + + + ASVLD + A-session valid + 18 + 1 + read-only + + + BSVLD + B-session valid + 19 + 1 + read-only + + + + + OTG_HS_GOTGINT + OTG_HS_GOTGINT + OTG_HS interrupt register + 0x4 + 32 + read-write + 0x0 + + + SEDET + Session end detected + 2 + 1 + + + SRSSCHG + Session request success status + change + 8 + 1 + + + HNSSCHG + Host negotiation success status + change + 9 + 1 + + + HNGDET + Host negotiation detected + 17 + 1 + + + ADTOCHG + A-device timeout change + 18 + 1 + + + DBCDNE + Debounce done + 19 + 1 + + + + + OTG_HS_GAHBCFG + OTG_HS_GAHBCFG + OTG_HS AHB configuration + register + 0x8 + 32 + read-write + 0x0 + + + GINT + Global interrupt mask + 0 + 1 + + + HBSTLEN + Burst length/type + 1 + 4 + + + DMAEN + DMA enable + 5 + 1 + + + TXFELVL + TxFIFO empty level + 7 + 1 + + + PTXFELVL + Periodic TxFIFO empty + level + 8 + 1 + + + + + OTG_HS_GUSBCFG + OTG_HS_GUSBCFG + OTG_HS USB configuration + register + 0xC + 32 + 0x00000A00 + + + TOCAL + FS timeout calibration + 0 + 3 + read-write + + + PHYSEL + USB 2.0 high-speed ULPI PHY or USB 1.1 + full-speed serial transceiver select + 6 + 1 + write-only + + + SRPCAP + SRP-capable + 8 + 1 + read-write + + + HNPCAP + HNP-capable + 9 + 1 + read-write + + + TRDT + USB turnaround time + 10 + 4 + read-write + + + PHYLPCS + PHY Low-power clock select + 15 + 1 + read-write + + + ULPIFSLS + ULPI FS/LS select + 17 + 1 + read-write + + + ULPIAR + ULPI Auto-resume + 18 + 1 + read-write + + + ULPICSM + ULPI Clock SuspendM + 19 + 1 + read-write + + + ULPIEVBUSD + ULPI External VBUS Drive + 20 + 1 + read-write + + + ULPIEVBUSI + ULPI external VBUS + indicator + 21 + 1 + read-write + + + TSDPS + TermSel DLine pulsing + selection + 22 + 1 + read-write + + + PCCI + Indicator complement + 23 + 1 + read-write + + + PTCI + Indicator pass through + 24 + 1 + read-write + + + ULPIIPD + ULPI interface protect + disable + 25 + 1 + read-write + + + FHMOD + Forced host mode + 29 + 1 + read-write + + + FDMOD + Forced peripheral mode + 30 + 1 + read-write + + + CTXPKT + Corrupt Tx packet + 31 + 1 + read-write + + + + + OTG_HS_GRSTCTL + OTG_HS_GRSTCTL + OTG_HS reset register + 0x10 + 32 + 0x20000000 + + + CSRST + Core soft reset + 0 + 1 + read-write + + + HSRST + HCLK soft reset + 1 + 1 + read-write + + + FCRST + Host frame counter reset + 2 + 1 + read-write + + + RXFFLSH + RxFIFO flush + 4 + 1 + read-write + + + TXFFLSH + TxFIFO flush + 5 + 1 + read-write + + + TXFNUM + TxFIFO number + 6 + 5 + read-write + + + DMAREQ + DMA request signal + 30 + 1 + read-only + + + AHBIDL + AHB master idle + 31 + 1 + read-only + + + + + OTG_HS_GINTSTS + OTG_HS_GINTSTS + OTG_HS core interrupt register + 0x14 + 32 + 0x04000020 + + + CMOD + Current mode of operation + 0 + 1 + read-only + + + MMIS + Mode mismatch interrupt + 1 + 1 + read-write + + + OTGINT + OTG interrupt + 2 + 1 + read-only + + + SOF + Start of frame + 3 + 1 + read-write + + + RXFLVL + RxFIFO nonempty + 4 + 1 + read-only + + + NPTXFE + Nonperiodic TxFIFO empty + 5 + 1 + read-only + + + GINAKEFF + Global IN nonperiodic NAK + effective + 6 + 1 + read-only + + + BOUTNAKEFF + Global OUT NAK effective + 7 + 1 + read-only + + + ESUSP + Early suspend + 10 + 1 + read-write + + + USBSUSP + USB suspend + 11 + 1 + read-write + + + USBRST + USB reset + 12 + 1 + read-write + + + ENUMDNE + Enumeration done + 13 + 1 + read-write + + + ISOODRP + Isochronous OUT packet dropped + interrupt + 14 + 1 + read-write + + + EOPF + End of periodic frame + interrupt + 15 + 1 + read-write + + + IEPINT + IN endpoint interrupt + 18 + 1 + read-only + + + OEPINT + OUT endpoint interrupt + 19 + 1 + read-only + + + IISOIXFR + Incomplete isochronous IN + transfer + 20 + 1 + read-write + + + PXFR_INCOMPISOOUT + Incomplete periodic + transfer + 21 + 1 + read-write + + + DATAFSUSP + Data fetch suspended + 22 + 1 + read-write + + + HPRTINT + Host port interrupt + 24 + 1 + read-only + + + HCINT + Host channels interrupt + 25 + 1 + read-only + + + PTXFE + Periodic TxFIFO empty + 26 + 1 + read-only + + + CIDSCHG + Connector ID status change + 28 + 1 + read-write + + + DISCINT + Disconnect detected + interrupt + 29 + 1 + read-write + + + SRQINT + Session request/new session detected + interrupt + 30 + 1 + read-write + + + WKUINT + Resume/remote wakeup detected + interrupt + 31 + 1 + read-write + + + + + OTG_HS_GINTMSK + OTG_HS_GINTMSK + OTG_HS interrupt mask register + 0x18 + 32 + 0x0 + + + MMISM + Mode mismatch interrupt + mask + 1 + 1 + read-write + + + OTGINT + OTG interrupt mask + 2 + 1 + read-write + + + SOFM + Start of frame mask + 3 + 1 + read-write + + + RXFLVLM + Receive FIFO nonempty mask + 4 + 1 + read-write + + + NPTXFEM + Nonperiodic TxFIFO empty + mask + 5 + 1 + read-write + + + GINAKEFFM + Global nonperiodic IN NAK effective + mask + 6 + 1 + read-write + + + GONAKEFFM + Global OUT NAK effective + mask + 7 + 1 + read-write + + + ESUSPM + Early suspend mask + 10 + 1 + read-write + + + USBSUSPM + USB suspend mask + 11 + 1 + read-write + + + USBRST + USB reset mask + 12 + 1 + read-write + + + ENUMDNEM + Enumeration done mask + 13 + 1 + read-write + + + ISOODRPM + Isochronous OUT packet dropped interrupt + mask + 14 + 1 + read-write + + + EOPFM + End of periodic frame interrupt + mask + 15 + 1 + read-write + + + EPMISM + Endpoint mismatch interrupt + mask + 17 + 1 + read-write + + + IEPINT + IN endpoints interrupt + mask + 18 + 1 + read-write + + + OEPINT + OUT endpoints interrupt + mask + 19 + 1 + read-write + + + IISOIXFRM + Incomplete isochronous IN transfer + mask + 20 + 1 + read-write + + + PXFRM_IISOOXFRM + Incomplete periodic transfer + mask + 21 + 1 + read-write + + + FSUSPM + Data fetch suspended mask + 22 + 1 + read-write + + + PRTIM + Host port interrupt mask + 24 + 1 + read-only + + + HCIM + Host channels interrupt + mask + 25 + 1 + read-write + + + PTXFEM + Periodic TxFIFO empty mask + 26 + 1 + read-write + + + CIDSCHGM + Connector ID status change + mask + 28 + 1 + read-write + + + DISCINT + Disconnect detected interrupt + mask + 29 + 1 + read-write + + + SRQIM + Session request/new session detected + interrupt mask + 30 + 1 + read-write + + + WUIM + Resume/remote wakeup detected interrupt + mask + 31 + 1 + read-write + + + + + OTG_HS_GRXSTSR_Host + OTG_HS_GRXSTSR_Host + OTG_HS Receive status debug read register + (host mode) + 0x1C + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXSTSP_Host + OTG_HS_GRXSTSP_Host + OTG_HS status read and pop register (host + mode) + 0x20 + 32 + read-only + 0x0 + + + CHNUM + Channel number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + + + OTG_HS_GRXFSIZ + OTG_HS_GRXFSIZ + OTG_HS Receive FIFO size + register + 0x24 + 32 + read-write + 0x00000200 + + + RXFD + RxFIFO depth + 0 + 16 + + + + + OTG_HS_GNPTXFSIZ_Host + OTG_HS_GNPTXFSIZ_Host + OTG_HS nonperiodic transmit FIFO size + register (host mode) + 0x28 + 32 + read-write + 0x00000200 + + + NPTXFSA + Nonperiodic transmit RAM start + address + 0 + 16 + + + NPTXFD + Nonperiodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_TX0FSIZ_Peripheral + OTG_HS_TX0FSIZ_Peripheral + Endpoint 0 transmit FIFO size (peripheral + mode) + OTG_HS_GNPTXFSIZ_Host + 0x28 + 32 + read-write + 0x00000200 + + + TX0FSA + Endpoint 0 transmit RAM start + address + 0 + 16 + + + TX0FD + Endpoint 0 TxFIFO depth + 16 + 16 + + + + + OTG_HS_GNPTXSTS + OTG_HS_GNPTXSTS + OTG_HS nonperiodic transmit FIFO/queue + status register + 0x2C + 32 + read-only + 0x00080200 + + + NPTXFSAV + Nonperiodic TxFIFO space + available + 0 + 16 + + + NPTQXSAV + Nonperiodic transmit request queue space + available + 16 + 8 + + + NPTXQTOP + Top of the nonperiodic transmit request + queue + 24 + 7 + + + + + OTG_HS_GCCFG + OTG_HS_GCCFG + OTG_HS general core configuration + register + 0x38 + 32 + read-write + 0x0 + + + PWRDWN + Power down + 16 + 1 + + + I2CPADEN + Enable I2C bus connection for the + external I2C PHY interface + 17 + 1 + + + VBUSASEN + Enable the VBUS sensing + device + 18 + 1 + + + VBUSBSEN + Enable the VBUS sensing + device + 19 + 1 + + + SOFOUTEN + SOF output enable + 20 + 1 + + + NOVBUSSENS + VBUS sensing disable + option + 21 + 1 + + + + + OTG_HS_CID + OTG_HS_CID + OTG_HS core ID register + 0x3C + 32 + read-write + 0x00001200 + + + PRODUCT_ID + Product ID field + 0 + 32 + + + + + OTG_HS_HPTXFSIZ + OTG_HS_HPTXFSIZ + OTG_HS Host periodic transmit FIFO size + register + 0x100 + 32 + read-write + 0x02000600 + + + PTXSA + Host periodic TxFIFO start + address + 0 + 16 + + + PTXFD + Host periodic TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF1 + OTG_HS_DIEPTXF1 + OTG_HS device IN endpoint transmit FIFO size + register + 0x104 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF2 + OTG_HS_DIEPTXF2 + OTG_HS device IN endpoint transmit FIFO size + register + 0x108 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF3 + OTG_HS_DIEPTXF3 + OTG_HS device IN endpoint transmit FIFO size + register + 0x11C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF4 + OTG_HS_DIEPTXF4 + OTG_HS device IN endpoint transmit FIFO size + register + 0x120 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF5 + OTG_HS_DIEPTXF5 + OTG_HS device IN endpoint transmit FIFO size + register + 0x124 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF6 + OTG_HS_DIEPTXF6 + OTG_HS device IN endpoint transmit FIFO size + register + 0x128 + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_DIEPTXF7 + OTG_HS_DIEPTXF7 + OTG_HS device IN endpoint transmit FIFO size + register + 0x12C + 32 + read-write + 0x02000400 + + + INEPTXSA + IN endpoint FIFOx transmit RAM start + address + 0 + 16 + + + INEPTXFD + IN endpoint TxFIFO depth + 16 + 16 + + + + + OTG_HS_GRXSTSR_Peripheral + OTG_HS_GRXSTSR_Peripheral + OTG_HS Receive status debug read register + (peripheral mode mode) + OTG_HS_GRXSTSR_Host + 0x1C + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + OTG_HS_GRXSTSP_Peripheral + OTG_HS_GRXSTSP_Peripheral + OTG_HS status read and pop register + (peripheral mode) + OTG_HS_GRXSTSP_Host + 0x20 + 32 + read-only + 0x0 + + + EPNUM + Endpoint number + 0 + 4 + + + BCNT + Byte count + 4 + 11 + + + DPID + Data PID + 15 + 2 + + + PKTSTS + Packet status + 17 + 4 + + + FRMNUM + Frame number + 21 + 4 + + + + + + + OTG_HS_HOST + USB on the go high speed + USB_OTG_HS + 0x40040400 + + 0x0 + 0x400 + registers + + + + OTG_HS_HCFG + OTG_HS_HCFG + OTG_HS host configuration + register + 0x0 + 32 + 0x0 + + + FSLSPCS + FS/LS PHY clock select + 0 + 2 + read-write + + + FSLSS + FS- and LS-only support + 2 + 1 + read-only + + + + + OTG_HS_HFIR + OTG_HS_HFIR + OTG_HS Host frame interval + register + 0x4 + 32 + read-write + 0x0000EA60 + + + FRIVL + Frame interval + 0 + 16 + + + RLDCTRL + Reload control + 16 + 1 + + + + + OTG_HS_HFNUM + OTG_HS_HFNUM + OTG_HS host frame number/frame time + remaining register + 0x8 + 32 + read-only + 0x00003FFF + + + FRNUM + Frame number + 0 + 16 + + + FTREM + Frame time remaining + 16 + 16 + + + + + OTG_HS_HPTXSTS + OTG_HS_HPTXSTS + OTG_HS_Host periodic transmit FIFO/queue + status register + 0x10 + 32 + 0x00080100 + + + PTXFSAVL + Periodic transmit data FIFO space + available + 0 + 16 + read-write + + + PTXQSAV + Periodic transmit request queue space + available + 16 + 8 + read-only + + + PTXQTOP + Top of the periodic transmit request + queue + 24 + 8 + read-only + + + + + OTG_HS_HAINT + OTG_HS_HAINT + OTG_HS Host all channels interrupt + register + 0x14 + 32 + read-only + 0x0 + + + HAINT + Channel interrupts + 0 + 16 + + + + + OTG_HS_HAINTMSK + OTG_HS_HAINTMSK + OTG_HS host all channels interrupt mask + register + 0x18 + 32 + read-write + 0x0 + + + HAINTM + Channel interrupt mask + 0 + 16 + + + + + OTG_HS_HPRT + OTG_HS_HPRT + OTG_HS host port control and status + register + 0x40 + 32 + 0x0 + + + PCSTS + Port connect status + 0 + 1 + read-only + + + PCDET + Port connect detected + 1 + 1 + read-write + + + PENA + Port enable + 2 + 1 + read-write + + + PENCHNG + Port enable/disable change + 3 + 1 + read-write + + + POCA + Port overcurrent active + 4 + 1 + read-only + + + POCCHNG + Port overcurrent change + 5 + 1 + read-write + + + PRES + Port resume + 6 + 1 + read-write + + + PSUSP + Port suspend + 7 + 1 + read-write + + + PRST + Port reset + 8 + 1 + read-write + + + PLSTS + Port line status + 10 + 2 + read-only + + + PPWR + Port power + 12 + 1 + read-write + + + PTCTL + Port test control + 13 + 4 + read-write + + + PSPD + Port speed + 17 + 2 + read-only + + + + + OTG_HS_HCCHAR0 + OTG_HS_HCCHAR0 + OTG_HS host channel-0 characteristics + register + 0x100 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR1 + OTG_HS_HCCHAR1 + OTG_HS host channel-1 characteristics + register + 0x120 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR2 + OTG_HS_HCCHAR2 + OTG_HS host channel-2 characteristics + register + 0x140 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR3 + OTG_HS_HCCHAR3 + OTG_HS host channel-3 characteristics + register + 0x160 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR4 + OTG_HS_HCCHAR4 + OTG_HS host channel-4 characteristics + register + 0x180 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR5 + OTG_HS_HCCHAR5 + OTG_HS host channel-5 characteristics + register + 0x1A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR6 + OTG_HS_HCCHAR6 + OTG_HS host channel-6 characteristics + register + 0x1C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR7 + OTG_HS_HCCHAR7 + OTG_HS host channel-7 characteristics + register + 0x1E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR8 + OTG_HS_HCCHAR8 + OTG_HS host channel-8 characteristics + register + 0x200 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR9 + OTG_HS_HCCHAR9 + OTG_HS host channel-9 characteristics + register + 0x220 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR10 + OTG_HS_HCCHAR10 + OTG_HS host channel-10 characteristics + register + 0x240 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR11 + OTG_HS_HCCHAR11 + OTG_HS host channel-11 characteristics + register + 0x260 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR12 + OTG_HS_HCCHAR12 + OTG_HS host channel-12 characteristics + register + 0x280 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR13 + OTG_HS_HCCHAR13 + OTG_HS host channel-13 characteristics + register + 0x2A0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR14 + OTG_HS_HCCHAR14 + OTG_HS host channel-14 characteristics + register + 0x2C0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCCHAR15 + OTG_HS_HCCHAR15 + OTG_HS host channel-15 characteristics + register + 0x2E0 + 32 + read-write + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + + + EPNUM + Endpoint number + 11 + 4 + + + EPDIR + Endpoint direction + 15 + 1 + + + LSDEV + Low-speed device + 17 + 1 + + + EPTYP + Endpoint type + 18 + 2 + + + MCNT + Multi Count (MC) / Error Count + (EC) + 20 + 2 + + + DAD + Device address + 22 + 7 + + + ODDFRM + Odd frame + 29 + 1 + + + CHDIS + Channel disable + 30 + 1 + + + CHENA + Channel enable + 31 + 1 + + + + + OTG_HS_HCSPLT0 + OTG_HS_HCSPLT0 + OTG_HS host channel-0 split control + register + 0x104 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT1 + OTG_HS_HCSPLT1 + OTG_HS host channel-1 split control + register + 0x124 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT2 + OTG_HS_HCSPLT2 + OTG_HS host channel-2 split control + register + 0x144 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT3 + OTG_HS_HCSPLT3 + OTG_HS host channel-3 split control + register + 0x164 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT4 + OTG_HS_HCSPLT4 + OTG_HS host channel-4 split control + register + 0x184 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT5 + OTG_HS_HCSPLT5 + OTG_HS host channel-5 split control + register + 0x1A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT6 + OTG_HS_HCSPLT6 + OTG_HS host channel-6 split control + register + 0x1C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT7 + OTG_HS_HCSPLT7 + OTG_HS host channel-7 split control + register + 0x1E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT8 + OTG_HS_HCSPLT8 + OTG_HS host channel-8 split control + register + 0x204 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT9 + OTG_HS_HCSPLT9 + OTG_HS host channel-9 split control + register + 0x224 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT10 + OTG_HS_HCSPLT10 + OTG_HS host channel-10 split control + register + 0x244 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT11 + OTG_HS_HCSPLT11 + OTG_HS host channel-11 split control + register + 0x264 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT12 + OTG_HS_HCSPLT12 + OTG_HS host channel-12 split control + register + 0x284 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT13 + OTG_HS_HCSPLT13 + OTG_HS host channel-13 split control + register + 0x2A4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT14 + OTG_HS_HCSPLT14 + OTG_HS host channel-14 split control + register + 0x2C4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCSPLT15 + OTG_HS_HCSPLT15 + OTG_HS host channel-15 split control + register + 0x2E4 + 32 + read-write + 0x0 + + + PRTADDR + Port address + 0 + 7 + + + HUBADDR + Hub address + 7 + 7 + + + XACTPOS + XACTPOS + 14 + 2 + + + COMPLSPLT + Do complete split + 16 + 1 + + + SPLITEN + Split enable + 31 + 1 + + + + + OTG_HS_HCINT0 + OTG_HS_HCINT0 + OTG_HS host channel-11 interrupt + register + 0x108 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT1 + OTG_HS_HCINT1 + OTG_HS host channel-1 interrupt + register + 0x128 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT2 + OTG_HS_HCINT2 + OTG_HS host channel-2 interrupt + register + 0x148 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT3 + OTG_HS_HCINT3 + OTG_HS host channel-3 interrupt + register + 0x168 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT4 + OTG_HS_HCINT4 + OTG_HS host channel-4 interrupt + register + 0x188 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT5 + OTG_HS_HCINT5 + OTG_HS host channel-5 interrupt + register + 0x1A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT6 + OTG_HS_HCINT6 + OTG_HS host channel-6 interrupt + register + 0x1C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT7 + OTG_HS_HCINT7 + OTG_HS host channel-7 interrupt + register + 0x1E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT8 + OTG_HS_HCINT8 + OTG_HS host channel-8 interrupt + register + 0x208 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT9 + OTG_HS_HCINT9 + OTG_HS host channel-9 interrupt + register + 0x228 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT10 + OTG_HS_HCINT10 + OTG_HS host channel-10 interrupt + register + 0x248 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT11 + OTG_HS_HCINT11 + OTG_HS host channel-11 interrupt + register + 0x268 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT12 + OTG_HS_HCINT12 + OTG_HS host channel-12 interrupt + register + 0x288 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT13 + OTG_HS_HCINT13 + OTG_HS host channel-13 interrupt + register + 0x2A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT14 + OTG_HS_HCINT14 + OTG_HS host channel-14 interrupt + register + 0x2C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINT15 + OTG_HS_HCINT15 + OTG_HS host channel-15 interrupt + register + 0x2E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + 0 + 1 + + + CHH + Channel halted + 1 + 1 + + + AHBERR + AHB error + 2 + 1 + + + STALL + STALL response received + interrupt + 3 + 1 + + + NAK + NAK response received + interrupt + 4 + 1 + + + ACK + ACK response received/transmitted + interrupt + 5 + 1 + + + NYET + Response received + interrupt + 6 + 1 + + + TXERR + Transaction error + 7 + 1 + + + BBERR + Babble error + 8 + 1 + + + FRMOR + Frame overrun + 9 + 1 + + + DTERR + Data toggle error + 10 + 1 + + + + + OTG_HS_HCINTMSK0 + OTG_HS_HCINTMSK0 + OTG_HS host channel-11 interrupt mask + register + 0x10C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK1 + OTG_HS_HCINTMSK1 + OTG_HS host channel-1 interrupt mask + register + 0x12C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK2 + OTG_HS_HCINTMSK2 + OTG_HS host channel-2 interrupt mask + register + 0x14C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK3 + OTG_HS_HCINTMSK3 + OTG_HS host channel-3 interrupt mask + register + 0x16C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK4 + OTG_HS_HCINTMSK4 + OTG_HS host channel-4 interrupt mask + register + 0x18C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK5 + OTG_HS_HCINTMSK5 + OTG_HS host channel-5 interrupt mask + register + 0x1AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK6 + OTG_HS_HCINTMSK6 + OTG_HS host channel-6 interrupt mask + register + 0x1CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK7 + OTG_HS_HCINTMSK7 + OTG_HS host channel-7 interrupt mask + register + 0x1EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK8 + OTG_HS_HCINTMSK8 + OTG_HS host channel-8 interrupt mask + register + 0x20C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK9 + OTG_HS_HCINTMSK9 + OTG_HS host channel-9 interrupt mask + register + 0x22C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK10 + OTG_HS_HCINTMSK10 + OTG_HS host channel-10 interrupt mask + register + 0x24C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK11 + OTG_HS_HCINTMSK11 + OTG_HS host channel-11 interrupt mask + register + 0x26C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK12 + OTG_HS_HCINTMSK12 + OTG_HS host channel-12 interrupt mask + register + 0x28C + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK13 + OTG_HS_HCINTMSK13 + OTG_HS host channel-13 interrupt mask + register + 0x2AC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK14 + OTG_HS_HCINTMSK14 + OTG_HS host channel-14 interrupt mask + register + 0x2CC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCINTMSK15 + OTG_HS_HCINTMSK15 + OTG_HS host channel-15 interrupt mask + register + 0x2EC + 32 + read-write + 0x0 + + + XFRCM + Transfer completed mask + 0 + 1 + + + CHHM + Channel halted mask + 1 + 1 + + + AHBERRM + AHB error + 2 + 1 + + + STALLM + STALL response received interrupt + mask + 3 + 1 + + + NAKM + NAK response received interrupt + mask + 4 + 1 + + + ACKM + ACK response received/transmitted + interrupt mask + 5 + 1 + + + NYET + response received interrupt + mask + 6 + 1 + + + TXERRM + Transaction error mask + 7 + 1 + + + BBERRM + Babble error mask + 8 + 1 + + + FRMORM + Frame overrun mask + 9 + 1 + + + DTERRM + Data toggle error mask + 10 + 1 + + + + + OTG_HS_HCTSIZ0 + OTG_HS_HCTSIZ0 + OTG_HS host channel-11 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ1 + OTG_HS_HCTSIZ1 + OTG_HS host channel-1 transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ2 + OTG_HS_HCTSIZ2 + OTG_HS host channel-2 transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ3 + OTG_HS_HCTSIZ3 + OTG_HS host channel-3 transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ4 + OTG_HS_HCTSIZ4 + OTG_HS host channel-4 transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ5 + OTG_HS_HCTSIZ5 + OTG_HS host channel-5 transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ6 + OTG_HS_HCTSIZ6 + OTG_HS host channel-6 transfer size + register + 0x1D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ7 + OTG_HS_HCTSIZ7 + OTG_HS host channel-7 transfer size + register + 0x1F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ8 + OTG_HS_HCTSIZ8 + OTG_HS host channel-8 transfer size + register + 0x210 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ9 + OTG_HS_HCTSIZ9 + OTG_HS host channel-9 transfer size + register + 0x230 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ10 + OTG_HS_HCTSIZ10 + OTG_HS host channel-10 transfer size + register + 0x250 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ11 + OTG_HS_HCTSIZ11 + OTG_HS host channel-11 transfer size + register + 0x270 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ12 + OTG_HS_HCTSIZ12 + OTG_HS host channel-12 transfer size + register + 0x290 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ13 + OTG_HS_HCTSIZ13 + OTG_HS host channel-13 transfer size + register + 0x2B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ14 + OTG_HS_HCTSIZ14 + OTG_HS host channel-14 transfer size + register + 0x2D0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCTSIZ15 + OTG_HS_HCTSIZ15 + OTG_HS host channel-15 transfer size + register + 0x2F0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + DPID + Data PID + 29 + 2 + + + + + OTG_HS_HCDMA0 + OTG_HS_HCDMA0 + OTG_HS host channel-0 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA1 + OTG_HS_HCDMA1 + OTG_HS host channel-1 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA2 + OTG_HS_HCDMA2 + OTG_HS host channel-2 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA3 + OTG_HS_HCDMA3 + OTG_HS host channel-3 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA4 + OTG_HS_HCDMA4 + OTG_HS host channel-4 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA5 + OTG_HS_HCDMA5 + OTG_HS host channel-5 DMA address + register + 0x1B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA6 + OTG_HS_HCDMA6 + OTG_HS host channel-6 DMA address + register + 0x1D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA7 + OTG_HS_HCDMA7 + OTG_HS host channel-7 DMA address + register + 0x1F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA8 + OTG_HS_HCDMA8 + OTG_HS host channel-8 DMA address + register + 0x214 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA9 + OTG_HS_HCDMA9 + OTG_HS host channel-9 DMA address + register + 0x234 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA10 + OTG_HS_HCDMA10 + OTG_HS host channel-10 DMA address + register + 0x254 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA11 + OTG_HS_HCDMA11 + OTG_HS host channel-11 DMA address + register + 0x274 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA12 + OTG_HS_HCDMA12 + OTG_HS host channel-12 DMA address + register + 0x294 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA13 + OTG_HS_HCDMA13 + OTG_HS host channel-13 DMA address + register + 0x2B4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA14 + OTG_HS_HCDMA14 + OTG_HS host channel-14 DMA address + register + 0x2D4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_HCDMA15 + OTG_HS_HCDMA15 + OTG_HS host channel-15 DMA address + register + 0x2F4 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + + + OTG_HS_DEVICE + USB on the go high speed + USB_OTG_HS + 0x40040800 + + 0x0 + 0x400 + registers + + + + OTG_HS_DCFG + OTG_HS_DCFG + OTG_HS device configuration + register + 0x0 + 32 + read-write + 0x02200000 + + + DSPD + Device speed + 0 + 2 + + + NZLSOHSK + Nonzero-length status OUT + handshake + 2 + 1 + + + DAD + Device address + 4 + 7 + + + PFIVL + Periodic (micro)frame + interval + 11 + 2 + + + PERSCHIVL + Periodic scheduling + interval + 24 + 2 + + + XCVRDLY + Transceiver delay + 14 + 1 + + + ERRATIM + Erratic error interrupt + mask + 15 + 1 + + + + + OTG_HS_DCTL + OTG_HS_DCTL + OTG_HS device control register + 0x4 + 32 + 0x0 + + + RWUSIG + Remote wakeup signaling + 0 + 1 + read-write + + + SDIS + Soft disconnect + 1 + 1 + read-write + + + GINSTS + Global IN NAK status + 2 + 1 + read-only + + + GONSTS + Global OUT NAK status + 3 + 1 + read-only + + + TCTL + Test control + 4 + 3 + read-write + + + SGINAK + Set global IN NAK + 7 + 1 + write-only + + + CGINAK + Clear global IN NAK + 8 + 1 + write-only + + + SGONAK + Set global OUT NAK + 9 + 1 + write-only + + + CGONAK + Clear global OUT NAK + 10 + 1 + write-only + + + POPRGDNE + Power-on programming done + 11 + 1 + read-write + + + + + OTG_HS_DSTS + OTG_HS_DSTS + OTG_HS device status register + 0x8 + 32 + read-only + 0x00000010 + + + SUSPSTS + Suspend status + 0 + 1 + + + ENUMSPD + Enumerated speed + 1 + 2 + + + EERR + Erratic error + 3 + 1 + + + FNSOF + Frame number of the received + SOF + 8 + 14 + + + + + OTG_HS_DIEPMSK + OTG_HS_DIEPMSK + OTG_HS device IN endpoint common interrupt + mask register + 0x10 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DOEPMSK + OTG_HS_DOEPMSK + OTG_HS device OUT endpoint common interrupt + mask register + 0x14 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + STUPM + SETUP phase done mask + 3 + 1 + + + OTEPDM + OUT token received when endpoint + disabled mask + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets received + mask + 6 + 1 + + + OPEM + OUT packet error mask + 8 + 1 + + + BOIM + BNA interrupt mask + 9 + 1 + + + + + OTG_HS_DAINT + OTG_HS_DAINT + OTG_HS device all endpoints interrupt + register + 0x18 + 32 + read-only + 0x0 + + + IEPINT + IN endpoint interrupt bits + 0 + 16 + + + OEPINT + OUT endpoint interrupt + bits + 16 + 16 + + + + + OTG_HS_DAINTMSK + OTG_HS_DAINTMSK + OTG_HS all endpoints interrupt mask + register + 0x1C + 32 + read-write + 0x0 + + + IEPM + IN EP interrupt mask bits + 0 + 16 + + + OEPM + OUT EP interrupt mask bits + 16 + 16 + + + + + OTG_HS_DVBUSDIS + OTG_HS_DVBUSDIS + OTG_HS device VBUS discharge time + register + 0x28 + 32 + read-write + 0x000017D7 + + + VBUSDT + Device VBUS discharge time + 0 + 16 + + + + + OTG_HS_DVBUSPULSE + OTG_HS_DVBUSPULSE + OTG_HS device VBUS pulsing time + register + 0x2C + 32 + read-write + 0x000005B8 + + + DVBUSP + Device VBUS pulsing time + 0 + 12 + + + + + OTG_HS_DTHRCTL + OTG_HS_DTHRCTL + OTG_HS Device threshold control + register + 0x30 + 32 + read-write + 0x0 + + + NONISOTHREN + Nonisochronous IN endpoints threshold + enable + 0 + 1 + + + ISOTHREN + ISO IN endpoint threshold + enable + 1 + 1 + + + TXTHRLEN + Transmit threshold length + 2 + 9 + + + RXTHREN + Receive threshold enable + 16 + 1 + + + RXTHRLEN + Receive threshold length + 17 + 9 + + + ARPEN + Arbiter parking enable + 27 + 1 + + + + + OTG_HS_DIEPEMPMSK + OTG_HS_DIEPEMPMSK + OTG_HS device IN endpoint FIFO empty + interrupt mask register + 0x34 + 32 + read-write + 0x0 + + + INEPTXFEM + IN EP Tx FIFO empty interrupt mask + bits + 0 + 16 + + + + + OTG_HS_DEACHINT + OTG_HS_DEACHINT + OTG_HS device each endpoint interrupt + register + 0x38 + 32 + read-write + 0x0 + + + IEP1INT + IN endpoint 1interrupt bit + 1 + 1 + + + OEP1INT + OUT endpoint 1 interrupt + bit + 17 + 1 + + + + + OTG_HS_DEACHINTMSK + OTG_HS_DEACHINTMSK + OTG_HS device each endpoint interrupt + register mask + 0x3C + 32 + read-write + 0x0 + + + IEP1INTM + IN Endpoint 1 interrupt mask + bit + 1 + 1 + + + OEP1INTM + OUT Endpoint 1 interrupt mask + bit + 17 + 1 + + + + + OTG_HS_DIEPEACHMSK1 + OTG_HS_DIEPEACHMSK1 + OTG_HS device each in endpoint-1 interrupt + register + 0x44 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask (nonisochronous + endpoints) + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + FIFO underrun mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + + + OTG_HS_DOEPEACHMSK1 + OTG_HS_DOEPEACHMSK1 + OTG_HS device each OUT endpoint-1 interrupt + register + 0x84 + 32 + read-write + 0x0 + + + XFRCM + Transfer completed interrupt + mask + 0 + 1 + + + EPDM + Endpoint disabled interrupt + mask + 1 + 1 + + + TOM + Timeout condition mask + 3 + 1 + + + ITTXFEMSK + IN token received when TxFIFO empty + mask + 4 + 1 + + + INEPNMM + IN token received with EP mismatch + mask + 5 + 1 + + + INEPNEM + IN endpoint NAK effective + mask + 6 + 1 + + + TXFURM + OUT packet error mask + 8 + 1 + + + BIM + BNA interrupt mask + 9 + 1 + + + BERRM + Bubble error interrupt + mask + 12 + 1 + + + NAKM + NAK interrupt mask + 13 + 1 + + + NYETM + NYET interrupt mask + 14 + 1 + + + + + OTG_HS_DIEPCTL0 + OTG_HS_DIEPCTL0 + OTG device endpoint-0 control + register + 0x100 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL1 + OTG_HS_DIEPCTL1 + OTG device endpoint-1 control + register + 0x120 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL2 + OTG_HS_DIEPCTL2 + OTG device endpoint-2 control + register + 0x140 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL3 + OTG_HS_DIEPCTL3 + OTG device endpoint-3 control + register + 0x160 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL4 + OTG_HS_DIEPCTL4 + OTG device endpoint-4 control + register + 0x180 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL5 + OTG_HS_DIEPCTL5 + OTG device endpoint-5 control + register + 0x1A0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL6 + OTG_HS_DIEPCTL6 + OTG device endpoint-6 control + register + 0x1C0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPCTL7 + OTG_HS_DIEPCTL7 + OTG device endpoint-7 control + register + 0x1E0 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even/odd frame + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + TXFNUM + TxFIFO number + 22 + 4 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DIEPINT0 + OTG_HS_DIEPINT0 + OTG device endpoint-0 interrupt + register + 0x108 + 32 + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT1 + OTG_HS_DIEPINT1 + OTG device endpoint-1 interrupt + register + 0x128 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT2 + OTG_HS_DIEPINT2 + OTG device endpoint-2 interrupt + register + 0x148 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT3 + OTG_HS_DIEPINT3 + OTG device endpoint-3 interrupt + register + 0x168 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT4 + OTG_HS_DIEPINT4 + OTG device endpoint-4 interrupt + register + 0x188 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT5 + OTG_HS_DIEPINT5 + OTG device endpoint-5 interrupt + register + 0x1A8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT6 + OTG_HS_DIEPINT6 + OTG device endpoint-6 interrupt + register + 0x1C8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPINT7 + OTG_HS_DIEPINT7 + OTG device endpoint-7 interrupt + register + 0x1E8 + 32 + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + read-write + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + read-write + + + TOC + Timeout condition + 3 + 1 + read-write + + + ITTXFE + IN token received when TxFIFO is + empty + 4 + 1 + read-write + + + INEPNE + IN endpoint NAK effective + 6 + 1 + read-write + + + TXFE + Transmit FIFO empty + 7 + 1 + read-only + + + TXFIFOUDRN + Transmit Fifo Underrun + 8 + 1 + read-write + + + BNA + Buffer not available + interrupt + 9 + 1 + read-write + + + PKTDRPSTS + Packet dropped status + 11 + 1 + read-write + + + BERR + Babble error interrupt + 12 + 1 + read-write + + + NAK + NAK interrupt + 13 + 1 + read-write + + + + + OTG_HS_DIEPTSIZ0 + OTG_HS_DIEPTSIZ0 + OTG_HS device IN endpoint 0 transfer size + register + 0x110 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 2 + + + + + OTG_HS_DIEPDMA1 + OTG_HS_DIEPDMA1 + OTG_HS device endpoint-1 DMA address + register + 0x114 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA2 + OTG_HS_DIEPDMA2 + OTG_HS device endpoint-2 DMA address + register + 0x134 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA3 + OTG_HS_DIEPDMA3 + OTG_HS device endpoint-3 DMA address + register + 0x154 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA4 + OTG_HS_DIEPDMA4 + OTG_HS device endpoint-4 DMA address + register + 0x174 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DIEPDMA5 + OTG_HS_DIEPDMA5 + OTG_HS device endpoint-5 DMA address + register + 0x194 + 32 + read-write + 0x0 + + + DMAADDR + DMA address + 0 + 32 + + + + + OTG_HS_DTXFSTS0 + OTG_HS_DTXFSTS0 + OTG_HS device IN endpoint transmit FIFO + status register + 0x118 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS1 + OTG_HS_DTXFSTS1 + OTG_HS device IN endpoint transmit FIFO + status register + 0x138 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS2 + OTG_HS_DTXFSTS2 + OTG_HS device IN endpoint transmit FIFO + status register + 0x158 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS3 + OTG_HS_DTXFSTS3 + OTG_HS device IN endpoint transmit FIFO + status register + 0x178 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS4 + OTG_HS_DTXFSTS4 + OTG_HS device IN endpoint transmit FIFO + status register + 0x198 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DTXFSTS5 + OTG_HS_DTXFSTS5 + OTG_HS device IN endpoint transmit FIFO + status register + 0x1B8 + 32 + read-only + 0x0 + + + INEPTFSAV + IN endpoint TxFIFO space + avail + 0 + 16 + + + + + OTG_HS_DIEPTSIZ1 + OTG_HS_DIEPTSIZ1 + OTG_HS device endpoint transfer size + register + 0x130 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ2 + OTG_HS_DIEPTSIZ2 + OTG_HS device endpoint transfer size + register + 0x150 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ3 + OTG_HS_DIEPTSIZ3 + OTG_HS device endpoint transfer size + register + 0x170 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ4 + OTG_HS_DIEPTSIZ4 + OTG_HS device endpoint transfer size + register + 0x190 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DIEPTSIZ5 + OTG_HS_DIEPTSIZ5 + OTG_HS device endpoint transfer size + register + 0x1B0 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + MCNT + Multi count + 29 + 2 + + + + + OTG_HS_DOEPCTL0 + OTG_HS_DOEPCTL0 + OTG_HS device control OUT endpoint 0 control + register + 0x300 + 32 + 0x00008000 + + + MPSIZ + Maximum packet size + 0 + 2 + read-only + + + USBAEP + USB active endpoint + 15 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-only + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-only + + + EPENA + Endpoint enable + 31 + 1 + write-only + + + + + OTG_HS_DOEPCTL1 + OTG_HS_DOEPCTL1 + OTG device endpoint-1 control + register + 0x320 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL2 + OTG_HS_DOEPCTL2 + OTG device endpoint-2 control + register + 0x340 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPCTL3 + OTG_HS_DOEPCTL3 + OTG device endpoint-3 control + register + 0x360 + 32 + 0x0 + + + MPSIZ + Maximum packet size + 0 + 11 + read-write + + + USBAEP + USB active endpoint + 15 + 1 + read-write + + + EONUM_DPID + Even odd frame/Endpoint data + PID + 16 + 1 + read-only + + + NAKSTS + NAK status + 17 + 1 + read-only + + + EPTYP + Endpoint type + 18 + 2 + read-write + + + SNPM + Snoop mode + 20 + 1 + read-write + + + Stall + STALL handshake + 21 + 1 + read-write + + + CNAK + Clear NAK + 26 + 1 + write-only + + + SNAK + Set NAK + 27 + 1 + write-only + + + SD0PID_SEVNFRM + Set DATA0 PID/Set even + frame + 28 + 1 + write-only + + + SODDFRM + Set odd frame + 29 + 1 + write-only + + + EPDIS + Endpoint disable + 30 + 1 + read-write + + + EPENA + Endpoint enable + 31 + 1 + read-write + + + + + OTG_HS_DOEPINT0 + OTG_HS_DOEPINT0 + OTG_HS device endpoint-0 interrupt + register + 0x308 + 32 + read-write + 0x00000080 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT1 + OTG_HS_DOEPINT1 + OTG_HS device endpoint-1 interrupt + register + 0x328 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT2 + OTG_HS_DOEPINT2 + OTG_HS device endpoint-2 interrupt + register + 0x348 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT3 + OTG_HS_DOEPINT3 + OTG_HS device endpoint-3 interrupt + register + 0x368 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT4 + OTG_HS_DOEPINT4 + OTG_HS device endpoint-4 interrupt + register + 0x388 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT5 + OTG_HS_DOEPINT5 + OTG_HS device endpoint-5 interrupt + register + 0x3A8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT6 + OTG_HS_DOEPINT6 + OTG_HS device endpoint-6 interrupt + register + 0x3C8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPINT7 + OTG_HS_DOEPINT7 + OTG_HS device endpoint-7 interrupt + register + 0x3E8 + 32 + read-write + 0x0 + + + XFRC + Transfer completed + interrupt + 0 + 1 + + + EPDISD + Endpoint disabled + interrupt + 1 + 1 + + + STUP + SETUP phase done + 3 + 1 + + + OTEPDIS + OUT token received when endpoint + disabled + 4 + 1 + + + B2BSTUP + Back-to-back SETUP packets + received + 6 + 1 + + + NYET + NYET interrupt + 14 + 1 + + + + + OTG_HS_DOEPTSIZ0 + OTG_HS_DOEPTSIZ0 + OTG_HS device endpoint-1 transfer size + register + 0x310 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 7 + + + PKTCNT + Packet count + 19 + 1 + + + STUPCNT + SETUP packet count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ1 + OTG_HS_DOEPTSIZ1 + OTG_HS device endpoint-2 transfer size + register + 0x330 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ2 + OTG_HS_DOEPTSIZ2 + OTG_HS device endpoint-3 transfer size + register + 0x350 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ3 + OTG_HS_DOEPTSIZ3 + OTG_HS device endpoint-4 transfer size + register + 0x370 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + OTG_HS_DOEPTSIZ4 + OTG_HS_DOEPTSIZ4 + OTG_HS device endpoint-5 transfer size + register + 0x390 + 32 + read-write + 0x0 + + + XFRSIZ + Transfer size + 0 + 19 + + + PKTCNT + Packet count + 19 + 10 + + + RXDPID_STUPCNT + Received data PID/SETUP packet + count + 29 + 2 + + + + + + + OTG_HS_PWRCLK + USB on the go high speed + USB_OTG_HS + 0x40040E00 + + 0x0 + 0x3F200 + registers + + + OTG_HS_WKUP + USB On The Go HS Wakeup + 76 + + + + OTG_HS_PCGCR + OTG_HS_PCGCR + Power and clock gating control + register + 0x0 + 32 + read-write + 0x0 + + + STPPCLK + Stop PHY clock + 0 + 1 + + + GATEHCLK + Gate HCLK + 1 + 1 + + + PHYSUSP + PHY suspended + 4 + 1 + + + + + + + SAI1 + Serial audio interface + SAI + 0x40015800 + + 0x0 + 0x400 + registers + + + SAI1 + SAI1 global interrupt + 87 + + + + BCR1 + BCR1 + BConfiguration register 1 + 0x24 + 0x20 + read-write + 0x00000040 + + + MCJDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIBEN + Audio block B enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + BCR2 + BCR2 + BConfiguration register 2 + 0x28 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + BFRCR + BFRCR + BFRCR + 0x2C + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + + + FSPOL + Frame synchronization + polarity + 17 + 1 + + + FSDEF + Frame synchronization + definition + 16 + 1 + + + FSALL + Frame synchronization active level + length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + BSLOTR + BSLOTR + BSlot register + 0x30 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + BIM + BIM + BInterrupt mask register2 + 0x34 + 0x20 + read-write + 0x00000000 + + + LFSDETIE + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDET + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + BSR + BSR + BStatus register + 0x38 + 0x20 + read-only + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + BCLRFR + BCLRFR + BClear flag register + 0x3C + 0x20 + write-only + 0x00000000 + + + LFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + BDR + BDR + BData register + 0x40 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + ACR1 + ACR1 + AConfiguration register 1 + 0x4 + 0x20 + read-write + 0x00000040 + + + MCJDIV + Master clock divider + 20 + 4 + + + NODIV + No divider + 19 + 1 + + + DMAEN + DMA enable + 17 + 1 + + + SAIAEN + Audio block A enable + 16 + 1 + + + OutDri + Output drive + 13 + 1 + + + MONO + Mono mode + 12 + 1 + + + SYNCEN + Synchronization enable + 10 + 2 + + + CKSTR + Clock strobing edge + 9 + 1 + + + LSBFIRST + Least significant bit + first + 8 + 1 + + + DS + Data size + 5 + 3 + + + PRTCFG + Protocol configuration + 2 + 2 + + + MODE + Audio block mode + 0 + 2 + + + + + ACR2 + ACR2 + AConfiguration register 2 + 0x8 + 0x20 + read-write + 0x00000000 + + + COMP + Companding mode + 14 + 2 + + + CPL + Complement bit + 13 + 1 + + + MUTECN + Mute counter + 7 + 6 + + + MUTEVAL + Mute value + 6 + 1 + + + MUTE + Mute + 5 + 1 + + + TRIS + Tristate management on data + line + 4 + 1 + + + FFLUS + FIFO flush + 3 + 1 + + + FTH + FIFO threshold + 0 + 3 + + + + + AFRCR + AFRCR + AFRCR + 0xC + 0x20 + read-write + 0x00000007 + + + FSOFF + Frame synchronization + offset + 18 + 1 + + + FSPOL + Frame synchronization + polarity + 17 + 1 + + + FSDEF + Frame synchronization + definition + 16 + 1 + + + FSALL + Frame synchronization active level + length + 8 + 7 + + + FRL + Frame length + 0 + 8 + + + + + ASLOTR + ASLOTR + ASlot register + 0x10 + 0x20 + read-write + 0x00000000 + + + SLOTEN + Slot enable + 16 + 16 + + + NBSLOT + Number of slots in an audio + frame + 8 + 4 + + + SLOTSZ + Slot size + 6 + 2 + + + FBOFF + First bit offset + 0 + 5 + + + + + AIM + AIM + AInterrupt mask register2 + 0x14 + 0x20 + read-write + 0x00000000 + + + LFSDET + Late frame synchronization detection + interrupt enable + 6 + 1 + + + AFSDETIE + Anticipated frame synchronization + detection interrupt enable + 5 + 1 + + + CNRDYIE + Codec not ready interrupt + enable + 4 + 1 + + + FREQIE + FIFO request interrupt + enable + 3 + 1 + + + WCKCFG + Wrong clock configuration interrupt + enable + 2 + 1 + + + MUTEDET + Mute detection interrupt + enable + 1 + 1 + + + OVRUDRIE + Overrun/underrun interrupt + enable + 0 + 1 + + + + + ASR + ASR + AStatus register + 0x18 + 0x20 + read-write + 0x00000000 + + + FLVL + FIFO level threshold + 16 + 3 + + + LFSDET + Late frame synchronization + detection + 6 + 1 + + + AFSDET + Anticipated frame synchronization + detection + 5 + 1 + + + CNRDY + Codec not ready + 4 + 1 + + + FREQ + FIFO request + 3 + 1 + + + WCKCFG + Wrong clock configuration flag. This bit + is read only. + 2 + 1 + + + MUTEDET + Mute detection + 1 + 1 + + + OVRUDR + Overrun / underrun + 0 + 1 + + + + + ACLRFR + ACLRFR + AClear flag register + 0x1C + 0x20 + read-write + 0x00000000 + + + LFSDET + Clear late frame synchronization + detection flag + 6 + 1 + + + CAFSDET + Clear anticipated frame synchronization + detection flag. + 5 + 1 + + + CNRDY + Clear codec not ready flag + 4 + 1 + + + WCKCFG + Clear wrong clock configuration + flag + 2 + 1 + + + MUTEDET + Mute detection flag + 1 + 1 + + + OVRUDR + Clear overrun / underrun + 0 + 1 + + + + + ADR + ADR + AData register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + GCR + GCR + Global configuration register + 0x0 + 0x20 + read-write + 0x00000000 + + + SYNCIN + Synchronization inputs + 0 + 2 + + + SYNCOUT + Synchronization outputs + 4 + 2 + + + + + + + SAI2 + 0x40015C00 + + SAI2 + SAI2 global interrupt + 91 + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR + CR + power control register + 0x0 + 0x20 + read-write + 0x0000C000 + + + LPDS + Low-power deep sleep + 0 + 1 + + + PDDS + Power down deepsleep + 1 + 1 + + + CWUF + Clear wakeup flag + 2 + 1 + + + CSBF + Clear standby flag + 3 + 1 + + + PVDE + Power voltage detector + enable + 4 + 1 + + + PLS + PVD level selection + 5 + 3 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + FPDS + Flash power down in Stop + mode + 9 + 1 + + + LPLVDS + Low-Power Regulator Low Voltage in + deepsleep + 10 + 1 + + + MRLVDS + Main regulator low voltage in deepsleep + mode + 11 + 1 + + + ADCDC1 + ADCDC1 + 13 + 1 + + + VOS + Regulator voltage scaling output + selection + 14 + 2 + + + ODEN + Over-drive enable + 16 + 1 + + + ODSWEN + Over-drive switching + enabled + 17 + 1 + + + UDEN + Under-drive enable in stop + mode + 18 + 2 + + + FMSSR + Flash Memory Stop while System + Run + 20 + 1 + + + FISSR + Flash Interface Stop while System + Run + 21 + 1 + + + + + CSR + CSR + power control/status register + 0x4 + 0x20 + 0x00000000 + + + WUF + Wakeup flag + 0 + 1 + read-only + + + SBF + Standby flag + 1 + 1 + read-only + + + PVDO + PVD output + 2 + 1 + read-only + + + BRR + Backup regulator ready + 3 + 1 + read-only + + + EWUP2 + Enable WKUP2 pin + 7 + 1 + read-write + + + EWUP + Enable WKUP pin + 8 + 1 + read-write + + + BRE + Backup regulator enable + 9 + 1 + read-write + + + VOSRDY + Regulator voltage scaling output + selection ready bit + 14 + 1 + read-only + + + ODRDY + Over-drive mode ready + 16 + 1 + read-only + + + ODSWRDY + Over-drive mode switching + ready + 17 + 1 + read-only + + + UDRDY + Under-drive ready flag + 18 + 2 + read-write + + + + + + + QUADSPI + QuadSPI interface + QUADSPI + 0xA0001000 + + 0x0 + 0x400 + registers + + + QuadSPI + QuadSPI global interrupt + 92 + + + + CR + CR + control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PRESCALER + Clock prescaler + 24 + 8 + + + PMM + Polling match mode + 23 + 1 + + + APMS + Automatic poll mode stop + 22 + 1 + + + TOIE + TimeOut interrupt enable + 20 + 1 + + + SMIE + Status match interrupt + enable + 19 + 1 + + + FTIE + FIFO threshold interrupt + enable + 18 + 1 + + + TCIE + Transfer complete interrupt + enable + 17 + 1 + + + TEIE + Transfer error interrupt + enable + 16 + 1 + + + FTHRES + IFO threshold level + 8 + 5 + + + FSEL + FLASH memory selection + 7 + 1 + + + DFM + Dual-flash mode + 6 + 1 + + + SSHIFT + Sample shift + 4 + 1 + + + TCEN + Timeout counter enable + 3 + 1 + + + DMAEN + DMA enable + 2 + 1 + + + ABORT + Abort request + 1 + 1 + + + EN + Enable + 0 + 1 + + + + + DCR + DCR + device configuration register + 0x4 + 0x20 + read-write + 0x00000000 + + + FSIZE + FLASH memory size + 16 + 5 + + + CSHT + Chip select high time + 8 + 3 + + + CKMODE + Mode 0 / mode 3 + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + read-only + 0x00000000 + + + FLEVEL + FIFO level + 8 + 7 + + + BUSY + Busy + 5 + 1 + + + TOF + Timeout flag + 4 + 1 + + + SMF + Status match flag + 3 + 1 + + + FTF + FIFO threshold flag + 2 + 1 + + + TCF + Transfer complete flag + 1 + 1 + + + TEF + Transfer error flag + 0 + 1 + + + + + FCR + FCR + flag clear register + 0xC + 0x20 + read-write + 0x00000000 + + + CTOF + Clear timeout flag + 4 + 1 + + + CSMF + Clear status match flag + 3 + 1 + + + CTCF + Clear transfer complete + flag + 1 + 1 + + + CTEF + Clear transfer error flag + 0 + 1 + + + + + DLR + DLR + data length register + 0x10 + 0x20 + read-write + 0x00000000 + + + DL + Data length + 0 + 32 + + + + + CCR + CCR + communication configuration + register + 0x14 + 0x20 + read-write + 0x00000000 + + + DDRM + Double data rate mode + 31 + 1 + + + DHHC + DDR hold half cycle + 30 + 1 + + + SIOO + Send instruction only once + mode + 28 + 1 + + + FMODE + Functional mode + 26 + 2 + + + DMODE + Data mode + 24 + 2 + + + DCYC + Number of dummy cycles + 18 + 5 + + + ABSIZE + Alternate bytes size + 16 + 2 + + + ABMODE + Alternate bytes mode + 14 + 2 + + + ADSIZE + Address size + 12 + 2 + + + ADMODE + Address mode + 10 + 2 + + + IMODE + Instruction mode + 8 + 2 + + + INSTRUCTION + Instruction + 0 + 8 + + + + + AR + AR + address register + 0x18 + 0x20 + read-write + 0x00000000 + + + ADDRESS + Address + 0 + 32 + + + + + ABR + ABR + ABR + 0x1C + 0x20 + read-write + 0x00000000 + + + ALTERNATE + ALTERNATE + 0 + 32 + + + + + DR + DR + data register + 0x20 + 0x20 + read-write + 0x00000000 + + + DATA + Data + 0 + 32 + + + + + PSMKR + PSMKR + polling status mask register + 0x24 + 0x20 + read-write + 0x00000000 + + + MASK + Status mask + 0 + 32 + + + + + PSMAR + PSMAR + polling status match register + 0x28 + 0x20 + read-write + 0x00000000 + + + MATCH + Status match + 0 + 32 + + + + + PIR + PIR + polling interval register + 0x2C + 0x20 + read-write + 0x00000000 + + + INTERVAL + Polling interval + 0 + 16 + + + + + LPTR + LPTR + low-power timeout register + 0x30 + 0x20 + read-write + 0x00000000 + + + TIMEOUT + Timeout period + 0 + 16 + + + + + + + SPDIF_RX + Receiver Interface + SPDIF_RX + 0x40004000 + + 0x0 + 0x400 + registers + + + SPDIF_Rx + SPDIF-Rx global interrupt + 94 + + + + CR + CR + Control register + 0x0 + 0x20 + read-write + 0x00000000 + + + SPDIFEN + Peripheral Block Enable + 0 + 2 + + + RXDMAEN + Receiver DMA ENable for data + flow + 2 + 1 + + + RXSTEO + STerEO Mode + 3 + 1 + + + DRFMT + RX Data format + 4 + 2 + + + PMSK + Mask Parity error bit + 6 + 1 + + + VMSK + Mask of Validity bit + 7 + 1 + + + CUMSK + Mask of channel status and user + bits + 8 + 1 + + + PTMSK + Mask of Preamble Type bits + 9 + 1 + + + CBDMAEN + Control Buffer DMA ENable for control + flow + 10 + 1 + + + CHSEL + Channel Selection + 11 + 1 + + + NBTR + Maximum allowed re-tries during + synchronization phase + 12 + 2 + + + WFA + Wait For Activity + 14 + 1 + + + INSEL + input selection + 16 + 3 + + + + + IMR + IMR + Interrupt mask register + 0x4 + 0x20 + read-write + 0x00000000 + + + RXNEIE + RXNE interrupt enable + 0 + 1 + + + CSRNEIE + Control Buffer Ready Interrupt + Enable + 1 + 1 + + + PERRIE + Parity error interrupt + enable + 2 + 1 + + + OVRIE + Overrun error Interrupt + Enable + 3 + 1 + + + SBLKIE + Synchronization Block Detected Interrupt + Enable + 4 + 1 + + + SYNCDIE + Synchronization Done + 5 + 1 + + + IFEIE + Serial Interface Error Interrupt + Enable + 6 + 1 + + + + + SR + SR + Status register + 0x8 + 0x20 + read-only + 0x00000000 + + + RXNE + Read data register not + empty + 0 + 1 + + + CSRNE + Control Buffer register is not + empty + 1 + 1 + + + PERR + Parity error + 2 + 1 + + + OVR + Overrun error + 3 + 1 + + + SBD + Synchronization Block + Detected + 4 + 1 + + + SYNCD + Synchronization Done + 5 + 1 + + + FERR + Framing error + 6 + 1 + + + SERR + Synchronization error + 7 + 1 + + + TERR + Time-out error + 8 + 1 + + + WIDTH5 + Duration of 5 symbols counted with + SPDIF_CLK + 16 + 15 + + + + + IFCR + IFCR + Interrupt Flag Clear register + 0xC + 0x20 + write-only + 0x00000000 + + + PERRCF + Clears the Parity error + flag + 2 + 1 + + + OVRCF + Clears the Overrun error + flag + 3 + 1 + + + SBDCF + Clears the Synchronization Block + Detected flag + 4 + 1 + + + SYNCDCF + Clears the Synchronization Done + flag + 5 + 1 + + + + + DR + DR + Data input register + 0x10 + 0x20 + read-only + 0x00000000 + + + DR + Parity Error bit + 0 + 24 + + + PE + Parity Error bit + 24 + 1 + + + V + Validity bit + 25 + 1 + + + U + User bit + 26 + 1 + + + C + Channel Status bit + 27 + 1 + + + PT + Preamble Type + 28 + 2 + + + + + CSR + CSR + Channel Status register + 0x14 + 0x20 + read-only + 0x00000000 + + + USR + User data information + 0 + 16 + + + CS + Channel A status + information + 16 + 8 + + + SOB + Start Of Block + 24 + 1 + + + + + DIR + DIR + Debug Information register + 0x18 + 0x20 + read-only + 0x00000000 + + + THI + Threshold HIGH + 0 + 13 + + + TLO + Threshold LOW + 16 + 13 + + + + + + + HDMI_CEC + HDMI-CEC controller + HDMI_CEC + 0x40006C00 + + 0x0 + 0x400 + registers + + + HDMI_CEC + HDMI-CEC global interrupt + 93 + + + + CEC_CR + CEC_CR + CEC control register + 0x0 + 0X20 + 0x00000000 + + + TXEOM + Tx End Of Message + 2 + 1 + read-only + + + TXSOM + Tx Start Of Message + 1 + 1 + read-only + + + CECEN + CEC Enable + 0 + 1 + read-write + + + + + CEC_CFGR + CEC_CFGR + CEC configuration register + 0x4 + 0X20 + read-write + 0x00000000 + + + LSTN + Listen mode + 31 + 1 + + + OAR + Own addresses + configuration + 16 + 15 + + + SFTOP + SFT Option Bit + 8 + 1 + + + BRDNOGEN + Avoid Error-Bit Generation in + Broadcast + 7 + 1 + + + LBPEGEN + Generate Error-Bit on Long Bit Period + Error + 6 + 1 + + + BREGEN + Generate Error-Bit on Bit Rising + Error + 5 + 1 + + + BRESTP + Rx-Stop on Bit Rising + Error + 4 + 1 + + + RXTOL + Rx-Tolerance + 3 + 1 + + + SFT + Signal Free Time + 0 + 3 + + + + + CEC_TXDR + CEC_TXDR + CEC Tx data register + 0x8 + 0X20 + write-only + 0x00000000 + + + TXD + Tx Data register + 0 + 8 + + + + + CEC_RXDR + CEC_RXDR + CEC Rx Data Register + 0xC + 0X20 + read-only + 0x00000000 + + + RXD + Rx Data register + 0 + 8 + + + + + CEC_ISR + CEC_ISR + CEC Interrupt and Status + Register + 0x10 + 0X20 + read-write + 0x00000000 + + + TXACKE + Tx-Missing Acknowledge + Error + 12 + 1 + + + TXERR + Tx-Error + 11 + 1 + + + TXUDR + Tx-Buffer Underrun + 10 + 1 + + + TXEND + End of Transmission + 9 + 1 + + + TXBR + Tx-Byte Request + 8 + 1 + + + ARBLST + Arbitration Lost + 7 + 1 + + + RXACKE + Rx-Missing Acknowledge + 6 + 1 + + + LBPE + Rx-Long Bit Period Error + 5 + 1 + + + SBPE + Rx-Short Bit Period Error + 4 + 1 + + + BRE + Rx-Bit Rising Error + 3 + 1 + + + RXOVR + Rx-Overrun + 2 + 1 + + + RXEND + End Of Reception + 1 + 1 + + + RXBR + Rx-Byte Received + 0 + 1 + + + + + CEC_IER + CEC_IER + CEC interrupt enable register + 0x14 + 0X20 + read-write + 0x00000000 + + + TXACKIE + Tx-Missing Acknowledge Error Interrupt + Enable + 12 + 1 + + + TXERRIE + Tx-Error Interrupt Enable + 11 + 1 + + + TXUDRIE + Tx-Underrun Interrupt + Enable + 10 + 1 + + + TXENDIE + Tx-End Of Message Interrupt + Enable + 9 + 1 + + + TXBRIE + Tx-Byte Request Interrupt + Enable + 8 + 1 + + + ARBLSTIE + Arbitration Lost Interrupt + Enable + 7 + 1 + + + RXACKIE + Rx-Missing Acknowledge Error Interrupt + Enable + 6 + 1 + + + LBPEIE + Long Bit Period Error Interrupt + Enable + 5 + 1 + + + SBPEIE + Short Bit Period Error Interrupt + Enable + 4 + 1 + + + BREIE + Bit Rising Error Interrupt + Enable + 3 + 1 + + + RXOVRIE + Rx-Buffer Overrun Interrupt + Enable + 2 + 1 + + + RXENDIE + End Of Reception Interrupt + Enable + 1 + 1 + + + RXBRIE + Rx-Byte Received Interrupt + Enable + 0 + 1 + + + + + + + SDIO + Secure digital input/output + interface + SDIO + 0x40012C00 + + 0x0 + 0x400 + registers + + + SDIO + SDIO global interrupt + 49 + + + + POWER + POWER + power control register + 0x0 + 0x20 + read-write + 0x00000000 + + + PWRCTRL + PWRCTRL + 0 + 2 + + + + + CLKCR + CLKCR + SDI clock control register + 0x4 + 0x20 + read-write + 0x00000000 + + + HWFC_EN + HW Flow Control enable + 14 + 1 + + + NEGEDGE + SDIO_CK dephasing selection + bit + 13 + 1 + + + WIDBUS + Wide bus mode enable bit + 11 + 2 + + + BYPASS + Clock divider bypass enable + bit + 10 + 1 + + + PWRSAV + Power saving configuration + bit + 9 + 1 + + + CLKEN + Clock enable bit + 8 + 1 + + + CLKDIV + Clock divide factor + 0 + 8 + + + + + ARG + ARG + argument register + 0x8 + 0x20 + read-write + 0x00000000 + + + CMDARG + Command argument + 0 + 32 + + + + + CMD + CMD + command register + 0xC + 0x20 + read-write + 0x00000000 + + + CE_ATACMD + CE-ATA command + 14 + 1 + + + nIEN + not Interrupt Enable + 13 + 1 + + + ENCMDcompl + Enable CMD completion + 12 + 1 + + + SDIOSuspend + SD I/O suspend command + 11 + 1 + + + CPSMEN + Command path state machine (CPSM) Enable + bit + 10 + 1 + + + WAITPEND + CPSM Waits for ends of data transfer + (CmdPend internal signal). + 9 + 1 + + + WAITINT + CPSM waits for interrupt + request + 8 + 1 + + + WAITRESP + Wait for response bits + 6 + 2 + + + CMDINDEX + Command index + 0 + 6 + + + + + RESPCMD + RESPCMD + command response register + 0x10 + 0x20 + read-only + 0x00000000 + + + RESPCMD + Response command index + 0 + 6 + + + + + RESP1 + RESP1 + response 1..4 register + 0x14 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS1 + Card Status + 0 + 32 + + + + + RESP2 + RESP2 + response 1..4 register + 0x18 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS2 + Card Status + 0 + 32 + + + + + RESP3 + RESP3 + response 1..4 register + 0x1C + 0x20 + read-only + 0x00000000 + + + CARDSTATUS3 + Card Status + 0 + 32 + + + + + RESP4 + RESP4 + response 1..4 register + 0x20 + 0x20 + read-only + 0x00000000 + + + CARDSTATUS4 + Card Status + 0 + 32 + + + + + DTIMER + DTIMER + data timer register + 0x24 + 0x20 + read-write + 0x00000000 + + + DATATIME + Data timeout period + 0 + 32 + + + + + DLEN + DLEN + data length register + 0x28 + 0x20 + read-write + 0x00000000 + + + DATALENGTH + Data length value + 0 + 25 + + + + + DCTRL + DCTRL + data control register + 0x2C + 0x20 + read-write + 0x00000000 + + + SDIOEN + SD I/O enable functions + 11 + 1 + + + RWMOD + Read wait mode + 10 + 1 + + + RWSTOP + Read wait stop + 9 + 1 + + + RWSTART + Read wait start + 8 + 1 + + + DBLOCKSIZE + Data block size + 4 + 4 + + + DMAEN + DMA enable bit + 3 + 1 + + + DTMODE + Data transfer mode selection 1: Stream + or SDIO multibyte data transfer. + 2 + 1 + + + DTDIR + Data transfer direction + selection + 1 + 1 + + + DTEN + DTEN + 0 + 1 + + + + + DCOUNT + DCOUNT + data counter register + 0x30 + 0x20 + read-only + 0x00000000 + + + DATACOUNT + Data count value + 0 + 25 + + + + + STA + STA + status register + 0x34 + 0x20 + read-only + 0x00000000 + + + CEATAEND + CE-ATA command completion signal + received for CMD61 + 23 + 1 + + + SDIOIT + SDIO interrupt received + 22 + 1 + + + RXDAVL + Data available in receive + FIFO + 21 + 1 + + + TXDAVL + Data available in transmit + FIFO + 20 + 1 + + + RXFIFOE + Receive FIFO empty + 19 + 1 + + + TXFIFOE + Transmit FIFO empty + 18 + 1 + + + RXFIFOF + Receive FIFO full + 17 + 1 + + + TXFIFOF + Transmit FIFO full + 16 + 1 + + + RXFIFOHF + Receive FIFO half full: there are at + least 8 words in the FIFO + 15 + 1 + + + TXFIFOHE + Transmit FIFO half empty: at least 8 + words can be written into the FIFO + 14 + 1 + + + RXACT + Data receive in progress + 13 + 1 + + + TXACT + Data transmit in progress + 12 + 1 + + + CMDACT + Command transfer in + progress + 11 + 1 + + + DBCKEND + Data block sent/received (CRC check + passed) + 10 + 1 + + + STBITERR + Start bit not detected on all data + signals in wide bus mode + 9 + 1 + + + DATAEND + Data end (data counter, SDIDCOUNT, is + zero) + 8 + 1 + + + CMDSENT + Command sent (no response + required) + 7 + 1 + + + CMDREND + Command response received (CRC check + passed) + 6 + 1 + + + RXOVERR + Received FIFO overrun + error + 5 + 1 + + + TXUNDERR + Transmit FIFO underrun + error + 4 + 1 + + + DTIMEOUT + Data timeout + 3 + 1 + + + CTIMEOUT + Command response timeout + 2 + 1 + + + DCRCFAIL + Data block sent/received (CRC check + failed) + 1 + 1 + + + CCRCFAIL + Command response received (CRC check + failed) + 0 + 1 + + + + + ICR + ICR + interrupt clear register + 0x38 + 0x20 + read-write + 0x00000000 + + + CEATAENDC + CEATAEND flag clear bit + 23 + 1 + + + SDIOITC + SDIOIT flag clear bit + 22 + 1 + + + DBCKENDC + DBCKEND flag clear bit + 10 + 1 + + + STBITERRC + STBITERR flag clear bit + 9 + 1 + + + DATAENDC + DATAEND flag clear bit + 8 + 1 + + + CMDSENTC + CMDSENT flag clear bit + 7 + 1 + + + CMDRENDC + CMDREND flag clear bit + 6 + 1 + + + RXOVERRC + RXOVERR flag clear bit + 5 + 1 + + + TXUNDERRC + TXUNDERR flag clear bit + 4 + 1 + + + DTIMEOUTC + DTIMEOUT flag clear bit + 3 + 1 + + + CTIMEOUTC + CTIMEOUT flag clear bit + 2 + 1 + + + DCRCFAILC + DCRCFAIL flag clear bit + 1 + 1 + + + CCRCFAILC + CCRCFAIL flag clear bit + 0 + 1 + + + + + MASK + MASK + mask register + 0x3C + 0x20 + read-write + 0x00000000 + + + CEATAENDIE + CE-ATA command completion signal + received interrupt enable + 23 + 1 + + + SDIOITIE + SDIO mode interrupt received interrupt + enable + 22 + 1 + + + RXDAVLIE + Data available in Rx FIFO interrupt + enable + 21 + 1 + + + TXDAVLIE + Data available in Tx FIFO interrupt + enable + 20 + 1 + + + RXFIFOEIE + Rx FIFO empty interrupt + enable + 19 + 1 + + + TXFIFOEIE + Tx FIFO empty interrupt + enable + 18 + 1 + + + RXFIFOFIE + Rx FIFO full interrupt + enable + 17 + 1 + + + TXFIFOFIE + Tx FIFO full interrupt + enable + 16 + 1 + + + RXFIFOHFIE + Rx FIFO half full interrupt + enable + 15 + 1 + + + TXFIFOHEIE + Tx FIFO half empty interrupt + enable + 14 + 1 + + + RXACTIE + Data receive acting interrupt + enable + 13 + 1 + + + TXACTIE + Data transmit acting interrupt + enable + 12 + 1 + + + CMDACTIE + Command acting interrupt + enable + 11 + 1 + + + DBCKENDIE + Data block end interrupt + enable + 10 + 1 + + + STBITERRIE + Start bit error interrupt + enable + 9 + 1 + + + DATAENDIE + Data end interrupt enable + 8 + 1 + + + CMDSENTIE + Command sent interrupt + enable + 7 + 1 + + + CMDRENDIE + Command response received interrupt + enable + 6 + 1 + + + RXOVERRIE + Rx FIFO overrun error interrupt + enable + 5 + 1 + + + TXUNDERRIE + Tx FIFO underrun error interrupt + enable + 4 + 1 + + + DTIMEOUTIE + Data timeout interrupt + enable + 3 + 1 + + + CTIMEOUTIE + Command timeout interrupt + enable + 2 + 1 + + + DCRCFAILIE + Data CRC fail interrupt + enable + 1 + 1 + + + CCRCFAILIE + Command CRC fail interrupt + enable + 0 + 1 + + + + + FIFOCNT + FIFOCNT + FIFO counter register + 0x48 + 0x20 + read-only + 0x00000000 + + + FIFOCOUNT + Remaining number of words to be written + to or read from the FIFO. + 0 + 24 + + + + + FIFO + FIFO + data FIFO register + 0x80 + 0x20 + read-write + 0x00000000 + + + FIFOData + Receive and transmit FIFO + data + 0 + 32 + + + + + + + diff --git a/sys/allowed_signers.sh b/sys/allowed_signers.sh new file mode 100755 index 0000000..eb4de92 --- /dev/null +++ b/sys/allowed_signers.sh @@ -0,0 +1,70 @@ +#!/bin/sh + +# Скрипт для обновления ключей для проверки подписей коммитов + +if ! git --version > /dev/null 2>&1; then + printf "\n\033[0;31mGIT is not found!\033[0m\n"; exit 1; +fi + +if ! git status > /dev/null 2>&1; then + printf "\n\033[0;31mThis is not a git repo!\033[0m\n"; exit 1; +fi + +domain=$(git remote -v | head -n 1 | tr '\t' ' ' | cut -d ' ' -f2) +domain=$(echo "$domain" | sed 's/.*@//' | sed 's/:.*//') + +echo "Repo domain: $domain" + +login=$1 +password=$2 + +if [ -z "$login" ]; then + printf "Enter login: " + read -r login +fi + +if [ -z "$password" ]; then + stty -echo + printf "Enter password: " + read -r password + stty echo + printf "\n" +fi + +apitest=$(curl -s -u "$login:$password" "https://$domain/api/v1/user") +# echo "apitest: $apitest" + +if echo "$apitest" | grep -- 'user does not exist' >/dev/null 2>&1; then + printf "\033[0;31mERROR: User \"%s\" does not exist on %s\033[0m\n" "$login" "$domain"; exit 1; +fi + +if echo "$apitest" | grep -- 'password is invalid' >/dev/null 2>&1; then + printf "\033[0;31mERROR: Invalid password\033[0m\n"; exit 1; +fi + +allowed_signers_file=~/.ssh/allowed_signers + +if [ ! -f "$allowed_signers_file" ]; then + echo "Create $allowed_signers_file" + touch $allowed_signers_file +fi + +users=$(git shortlog -snc --all | tr '\t' ' ' | sed 's/^ *//' | cut -d ' ' -f2) +echo "Repo users: $users" | tr "\n" ' '; echo + +echo "" > test.txt +for user in $users; do + keys=$(curl -s -u "$login:$password" "https://$domain/api/v1/users/$user/keys") + keys=$(echo "$keys" | tr , '\n' | grep -E -- '^"key":".*' | sed 's/^"key"://' | tr -d '\n') + + IFS='"' + for key in $keys; do + if [ "$key" = "" ]; then continue; fi + if grep -Fq "$key" "$allowed_signers_file"; then continue; fi + echo "New key for $user" + printf "%s %s\n" "$user" "$key" >> $allowed_signers_file + done + unset IFS +done + +echo "$allowed_signers_file updated" \ No newline at end of file diff --git a/sys/changelog.sh b/sys/changelog.sh new file mode 100755 index 0000000..3adaad0 --- /dev/null +++ b/sys/changelog.sh @@ -0,0 +1,38 @@ +#!/bin/sh + +# Скрипт генерирует changelog от последнего релиза. + +CHANGELOG=CHANGELOG.md + +printf "\033[0;32m~~~ %s generation ~~~\033[0m\n" "$CHANGELOG"; + +if ! git --version > /dev/null 2>&1; then + printf "\n\033[0;31mGIT is not found!\033[0m\n"; exit 1; +fi + +if ! git status > /dev/null 2>&1; then + printf "\n\033[0;31mThis is not a git repo!\033[0m\n"; exit 1; +fi + +# Get all tags that points to the HEAD +CURRENT_TAG=$(git tag --points-at HEAD) +echo "Current tag: $CURRENT_TAG" + +LAST_TAG=$(git describe --tags --abbrev=0 HEAD^ 2> /dev/null) +echo "Last tag: $LAST_TAG" + +if [ -n "$CURRENT_TAG" ]; then + printf "
changelog:\n\n" > $CHANGELOG +else + printf "Current commit does not have a release tag.\n\n" > $CHANGELOG +fi + +if [ -n "$LAST_TAG" ]; then + git log --pretty="- %h %s" "$LAST_TAG..HEAD" >> $CHANGELOG +else + git log --pretty="- %h %s" >> $CHANGELOG +fi + +if [ -n "$CURRENT_TAG" ]; then + printf "
" >> $CHANGELOG +fi \ No newline at end of file diff --git a/sys/export.bat b/sys/export.bat new file mode 100644 index 0000000..249d08f --- /dev/null +++ b/sys/export.bat @@ -0,0 +1,4 @@ +@echo off +chcp 65001 > nul +set "PATH=%USERPROFILE%\.xpack-dev-tools\xpack-windows-build-tools-4.4.1-2\bin;%PATH%" +set "PATH=%USERPROFILE%\.xpack-dev-tools\xpack-arm-none-eabi-gcc-12.3.1-1.2\bin;%PATH%" diff --git a/sys/export.ps1 b/sys/export.ps1 new file mode 100644 index 0000000..1c798c5 --- /dev/null +++ b/sys/export.ps1 @@ -0,0 +1,3 @@ +chcp 65001 > $null +$env:PATH = "$env:UserProfile\.xpack-dev-tools\xpack-windows-build-tools-4.4.1-2\bin;" + $env:PATH +$env:PATH = "$env:UserProfile\.xpack-dev-tools\xpack-arm-none-eabi-gcc-12.3.1-1.2\bin;" + $env:PATH diff --git a/sys/export.sh b/sys/export.sh new file mode 100644 index 0000000..19ca6f6 --- /dev/null +++ b/sys/export.sh @@ -0,0 +1,17 @@ +# This script should be sourced, not executed. +# shellcheck disable=SC2148,SC1091,SC3010 + +if echo "$0" | grep -- "bash" >/dev/null; then + if [ -f "$HOME/.bash_profile" ]; then . "$HOME/.bash_profile"; fi +fi + +if uname | grep -- "MINGW64" >/dev/null 2>&1; then + chcp.com 65001 > /dev/null + PATH=~/.xpack-dev-tools/xpack-windows-build-tools-4.4.1-2/bin:$PATH +fi + +if uname | grep -- "Darwin" >/dev/null 2>&1; then + PATH=/opt/homebrew/opt/make/libexec/gnubin:$PATH +fi + +PATH=~/.xpack-dev-tools/xpack-arm-none-eabi-gcc-12.3.1-1.2/bin:$PATH diff --git a/sys/export.zsh b/sys/export.zsh new file mode 100644 index 0000000..14bbc18 --- /dev/null +++ b/sys/export.zsh @@ -0,0 +1,4 @@ +# This script should be sourced, not executed. + +export PATH=/opt/homebrew/opt/make/libexec/gnubin:$PATH +export PATH=~/.xpack-dev-tools/xpack-arm-none-eabi-gcc-12.3.1-1.2/bin:$PATH diff --git a/sys/hex2fw.sh b/sys/hex2fw.sh new file mode 100755 index 0000000..66048fc --- /dev/null +++ b/sys/hex2fw.sh @@ -0,0 +1,184 @@ +#!/bin/sh +# shellcheck disable=SC2034,SC2317 +# Скрипт преобразования hex в fw. +# В качестве параметра принимает путь к файлу hex. + +# https://srecord.sourceforge.net/ +# https://manpages.ubuntu.com/manpages/xenial/man1/srec_cat.1.html +# https://manpages.ubuntu.com/manpages/xenial/man1/srec_examples.1.html + + +# echo -e "\033[0;32m~~~ Hex to FW ~~~\033[0m"; + +PATH=$(pwd)/$(dirname "$0")/srecord:$PATH +PATH="C:/Program Files/Git/usr/bin/":$PATH + +#========================== Functions ========================== +# ByteString - ascii string with bytes separated by spaces like "00 11 22 33" + +HexStringToByteString() { printf "%s" "$1" | od -An -t x1 | tr -d '\n' | tr 'a-f' 'A-F' | awk '{$1=$1};1' | tr -d '\n'; } + +GetRandomByteString() { openssl rand "$1" | od -An -t x1 | tr -d '\n' | tr 'a-f' 'A-F' | awk '{$1=$1};1' | tr -d '\n'; } + +IntelHexFileToByteString() +{ + T=$(srec_cat "$1" -intel -fill 0xFF -over "$1" -intel -address-length=4 -o - -ascii_hex) + res1=0x$(echo "$T" | head -n 1 | cut -f1 -d , | sed "s/.*\$A//") # Output: start addr + T=$(echo "$T" | tr -d '\r' | tr '\n' ' ' | tr '\002\003' ',') + T=$(echo "$T" | cut -f3 -d , | awk '{$1=$1};1') # (awk '{$1=$1};1' - remove leading, trailing and extra spaces between fields) + res2=$(echo "$T" | wc -w) # Output: size in bytes + res3=$T # Output: byte string +} + +# parmeters: addr fieldsnum string +GetFieldsFromByteString() { echo "$3" | cut -d ' ' -f "$1"-$(($1 + $2 - 1)); } + +# parmeters: addr fieldsnum string +GetHexFromByteString() { printf 0x; GetFieldsFromByteString "$1" "$2" "$3" | awk '{print $4,$3,$2,$1}' | tr -d ' '; } + +# parmeters: addr fieldsnum string +GetStringFromByteString() { GetFieldsFromByteString "$1" "$2" "$3" | xxd -r -p | tr -d '\000'; } + +ByteStringToAsciiHex() +{ + printf "\002 \$A%08X,\n" "$1" # Start and Address + echo "$2" | fold -s -w48 | awk '{$1=$1};1' # Data (awk '{$1=$1};1' - remove leading, trailing and extra spaces between fields) + printf "\003" # The End +} + +CRC32_FromByteString() +{ + # CAN прошивка использует кривой MPEG2 CRC32 по историческим причинам + # В будущем надо исправить на нормальный CRC32 от STM32 + T=$(ByteStringToAsciiHex 0x10000000 "$1") + T=$(echo "$T" | srec_cat - -ascii_hex -Bit_Reverse 4 -stm32 0 -Bit_Reverse 4 -xor 0xFF -o -ascii_hex) + echo "$T" | tr -d '\002\003' | head -n 2 | tail -n 1 | cut -d ' ' -f1-4 +} + +HexToByteString() { echo "$1" | sed 's/^0x//' | fold -w2 | tac | tr '\n' ' ' | sed 's/ $//'; } + +#========================== Main code ========================== + +IntelHexFileToByteString "$1" +fw_start_addr=$res1 +# echo "fw_start_addr $fw_start_addr" +fw_size=$res2 +# echo "fw_size $fw_size" +fw_data=$res3 +# echo "fw_data: $fw_data" + +# выкидываем последние 4 байта и дописываем наше CRC +fw_data=$(GetFieldsFromByteString 1 $((fw_size - 4)) "$fw_data") +crc=$(CRC32_FromByteString "$fw_data") +fw_data="$fw_data $crc" +# echo "fw_data: $fw_data" + +struct_addr=$(GetHexFromByteString 1 4 "$fw_data") +# echo "struct_addr $struct_addr" +struct_offset=$(( struct_addr - fw_start_addr )) +# echo "struct_offset $struct_offset" + +# // Структура массива информации о CAN-прошивке +# struct TCanFwInfo { +# TVersion Version; // Версия ПО +# uint32_t Build; // Хеш коммита в репозитории git +# uint32_t const * pCRC32; // Адрес, где расположена CRC32 +# uint32_t reserved2; +# uint8_t TextInfo[64]; // Текстовая информация +# } __attribute__((packed, aligned(4))); + +# // описание прошивки +# const TCanFwInfo gCanFwInfo = +# { +# (CAN_FW_VERSION << 24) | BUILD_DATE, // Version - Версия ПО +# GIT_BUILD, // Хеш коммита в репозитории git +# &CanChksum, // *pCRC32 - Адрес, где расположена CRC32 +# 0, // reserved2 +# M_NAME CAN_FW_DESCRIPTION "_" GIT_VERSION // TextInfo[64] - Текстовая информация +# }; + +index=$(( struct_offset + 1 )) +day=$(GetFieldsFromByteString "$index" 1 "$fw_data") +# echo "day: $day" + +index=$(( index + 1 )) +mounth=$(GetFieldsFromByteString "$index" 1 "$fw_data") +# echo "mounth: $mounth" + +index=$(( index + 1 )) +year=$(GetFieldsFromByteString "$index" 1 "$fw_data") +# echo "year: $year" + +index=$(( index + 1 )) +can_fw_version=$(GetFieldsFromByteString "$index" 1 "$fw_data") +# echo "can_fw_version: $can_fw_version" + +index=$(( index + 1 )) +git_build=$(GetFieldsFromByteString "$index" 4 "$fw_data") +# echo "git_build: $git_build" + +index=$(( index + 4 )) +CRC_addr=$(GetHexFromByteString "$index" 4 "$fw_data") +# echo "CRC_addr: $CRC_addr" + +index=$(( index + 8 )) +text_info=$(GetStringFromByteString "$index" 64 "$fw_data") +# echo "text_info: $text_info" + +# Версия git в последнем поле после '_' +git_version=$(echo "$text_info" | awk -F '_' '{print $NF}') +# echo "git_version: $git_version" + +# struct TFirmwareHdr { +# uint32_t ChckSum; // вычисляется по всем нижеследующим полям и данным +# uint32_t Type; // тип прошивки +# uint32_t Version; // версия/дата +# uint32_t Build; // Билд прошивки +# uint32_t Len; // длина данных +# uint32_t Offset; // смещение прошивки во flash +# uint8_t InitVect[8]; // Случайное число, используется при дешифровании +# }; // sizeof() = 32 + +# struct TFirmwareFileHdr { +# uint8_t Sign[8]; // fixed to 'MOBICAR ' +# uint8_t Desc[64]; // текстовое описание +# uint8_t pad1[24]; // дополнение до 96 байт +# TFirmwareHdr bin_hdr; +# }; // sizeof() = 128 + +# hdr1 - заголовок до CRC +hdr1="MOBICAR version $can_fw_version$year$mounth$day, $day.$mounth.$year, GIT = $git_version" +# echo "hdr1: $hdr1" +length=$(( ${#hdr1} )) +# echo "length: $length" +hdr1=$(HexStringToByteString "$hdr1") + +# Добиваем остаток до TFirmwarehdr (8+64+24=96) +for i in $(seq $(( length + 1 )) 96); do + hdr1="$hdr1 00" +done +# printf "hdr1:\n%s\n" "$hdr1" + +# hdr2 - заголовок после CRC +hdr2="02 00 00 00" # тип прошивки (CAN) +hdr2="$hdr2 $day $mounth $year $can_fw_version" # версия/дата +hdr2="$hdr2 $git_build" # Хеш коммита в репозитории git +len=$(printf "%08X" "$fw_size") # Len (Длина данных) +len=$(HexToByteString "$len") +hdr2="$hdr2 $len" +offset=$(printf "%08X" "$fw_start_addr") # offset (смещение прошивки во flash) +offset=$(HexToByteString "$offset") +hdr2="$hdr2 $offset" +rand=$(GetRandomByteString 8) +# echo "rand: $rand" +hdr2="$hdr2 $rand" +# printf "hdr2:\n%s\n" "$hdr2" + +crc=$(CRC32_FromByteString "$hdr2 $fw_data") +# printf "crc:\n%s\n" "$crc" +fw="$hdr1 $crc $hdr2 $fw_data" +# printf "fw:\n%s\n" "$fw" | fold -w48 + +fw_path="$(dirname "$1")/$text_info.fw" +printf "Generate \033[0;32m%s\033[0m\n" "$fw_path" +ByteStringToAsciiHex 0 "$fw" | srec_cat - -ascii_hex -o "$fw_path" -binary diff --git a/sys/info/JLink_drivers_install.png b/sys/info/JLink_drivers_install.png new file mode 100644 index 0000000000000000000000000000000000000000..3b1bbbdf5f4b2003f46159277228f3f87af789a5 GIT binary patch literal 6191 zcma)gWmr^Q+x7-QKm-wGP>E5IF6m}yL>iRt5=4d$iJ@CSa_FIkkOq-v5QPy?q`L+r zq?-W-e8=a0kMB6X`}=-8KlWOC{kYa%dtGs!*BPy)p-ge(!3_WaC{&&)=l}o#1pl5v zdL2I+rbun!CjxgJWjUZ~fc`grLG(&iT^0ap6UcFv#P~It%QHiF0HFNx_aQ(#m)ZaT z?N=2A*%v-$+c}zVMxI@u5m!Xi^q?EQ-4p~!qz)S?@h8%zq&-%+UO_wbR+J9qnFMc8`u^dXXAn>37^%J1834SF;N3UA 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b*8dQ6pb+nQQkbOiB0r#_sG(3LXA$y0d<^@n literal 0 HcmV?d00001 diff --git a/sys/info/install.md b/sys/info/install.md new file mode 100644 index 0000000..2d5f304 --- /dev/null +++ b/sys/info/install.md @@ -0,0 +1,108 @@ +## Подготовка к работе + +Предварительно должен быть установлен и настроен [Git for Windows 64-bit](https://git-scm.com/download/win). + +Также должны быть установлены 64-bit драйверы J-Link в папку `C:/Program Files/SEGGER/JLink/` +* Update existing installation +* Install for all users + +![alt text](JLink_drivers_install.png) + +--- + +### Установка Dev Tools +Запускаем скрипт [sys/install.sh](../../sys/install.sh) + +Произойдет скачивание и распаковка архивов с build tools и toolchain в папку `С:/xpack-dev-tools`. Никакие переменные среды не меняются, установка полностью независима (портативная) и не затрагивает никакие другие программы. + +После установки Dev Tools необходимо перезапустить VSCode если он был запущен. + +--- + +### Установка VSCode + +Скачиваем и устанавливаем [стабильную версию](https://code.visualstudio.com/). +- Открываем папку с нашим проектом в VSCode. +- Открываем расширения `Ctrl+Shift+X`. +- Устанавливаем расширения рекомендованные нашим `workspace`. Они помечены текстом `This extension is recommended by users of the current workspace.` +- [C/C++](vscode:extension/ms-vscode.cpptools) и [Cortex-Debug](vscode:extension/marus25.cortex-debug) обязательны к установке, остальные по желанию. + +Дополнительные расширения: +- [Git Graph](vscode:extension/mhutchie.git-graph) - рекомендую для работы с git. +- [LinkerScript](vscode:extension/ZixuanWang.linkerscript) - Linker Script files syntax. +- [GNU Linker Map files](vscode:extension/trond-snekvik.gnu-mapfiles) - Linker Map files syntax. +- [Intel HEX format](vscode:extension/keroc.hex-fmt) - Intel Hex files syntax. +- [Hex Editor](vscode:extension/ms-vscode.hexeditor) - Hex editor for binary files. +- [Arm Assembly](vscode:extension/dan-c-underwood.arm) - ARM Assembly files syntax. +- [Material Icon Theme](vscode:extension/pkief.material-icon-theme) - Симпатичные иконки файлов и папок в Explorer слева. +- [EditorConfig for VS Code](vscode:extension/EditorConfig.EditorConfig) - Следит за табами/пробелами/отступами/кодировкой для всех файлов проекта. +- [Open in External App](vscode:extension/YuTengjing.open-in-external-app) - Позволяет открывать файлы проекта в системных приложениях прямо из VSCode. +- [Task Buttons](vscode:extension/spencerwmiles.vscode-task-buttons) - Отображает кнопки для запуска тасков в статусбаре. + +Рекомендации всех расширений находятся в файле [.vscode/extensions.json](../../.vscode/extensions.json). + +--- + +### Сборка проекта в консоли +Сборка осуществяется с помощью `make`. + +В папке `settings` находятся скрипты экспорта переменных окружения: +- [sys/export.sh](../../sys/export.sh) - для bash +- [sys/export.bat](../../sys/export.bat) - для cmd +- [sys/export.ps1](../../sys/export.ps1) - для powershell + +Чтобы все наши компиляторы/линкеры/утилиты да и сам `make` стали доступными, вначале необходимо запустить соответствующий скрипт экспорта. + +Для bash запускаем через точку `. sys/export.sh`. Для остальных достаточно просто запустить скрипт. + +Далее просто запускаем нужный `make` таргет. + +#### Команды `make` +- `make -e MODEL=M2 debug` - сборка дебага M2 +- `make -e MODEL=M3 debug` - сборка дебага M3 +- `make -e MODEL=M2 release` - сборка релиза M2 +- `make -e MODEL=M3 release` - сборка релиза M3 + +Релизные сборки отличаются отключеным дефайном `DEBUG` и оптимизацией кода по размеру. + +--- + +### Сборка проекта в консоли VSCode +Тут проще: +- Открываем папку с нашим проектом в VSCode. +- Открываем консоль `Ctrl+~`. (запустится терминал по молчанию) +- Можете выбрать свой любимый терминал. Я предпочитаю `Git Bash`. +- И сразу можем набирать команды `make`. + +В файле [.vscode/settings.json](../../.vscode/settings.json) находятся конфигурации встроенных терминалов которые автоматически подгружают скрипты экспорта при открытии. + +--- + +### Сборка проекта с помощью VSCode Tasks. +- Открываем папку с нашим проектом в VSCode. +- Нажимаем `Ctrl+Shift+B` и выбираем нужный Task. + +Таски находятся в файле [.vscode/tasks.json](../../.vscode/tasks.json). Они автоматически загружают экспорт окружения и запускают нужные команды `make`. + +Если установлено расширение [Task Buttons](vscode:extension/spencerwmiles.vscode-task-buttons), то в строке статуса появятся кнопки для удобного запуска тасков `M2 Release`, `M3 Release`, `M2 Debug`, `M3 Debug`, `Clean`. + +--- + +### Отладка VSCode +В разделе `Run and Debug` слева выбираем конфигурацию отладки `Debug M2` или `Debug M3` и нажимаем зеленую стрелочку `Start Debugging` или `F5`. + +Проект автоматически соберется (preLaunchTask), прошьется МК и запустится отладка. + +Вывод логов доступен в терминале `SWO:ITM`. + +В дальнейшем если конфигурация ранее уже была выбрана, то для запуска компиляции и отладки достаточно просто нажимать `F5`. + +--- + +### PowerShell (если возникает ошибка) +В PowerShell по умолчанию отключено выполнение скриптов. Для исправления: +- Открываем PowerShell от имени администратора. +- Пишем и запускаем: `Set-ExecutionPolicy RemoteSigned` +- На вопрос отвечаем: A (Да для всех) + +--- \ No newline at end of file diff --git a/sys/install.sh b/sys/install.sh new file mode 100755 index 0000000..fd51325 --- /dev/null +++ b/sys/install.sh @@ -0,0 +1,103 @@ +#!/bin/sh +# shellcheck disable=SC2034 + +# This script installs dev tools (build tools & toolchain) + +# https://github.com/xpack-dev-tools/windows-build-tools-xpack/releases +# https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases + + +build_tools_version="4.4.1-2" # For Windows only +toolchain_version="12.3.1-1.2" # For all OS + +############################################################################################### + +install_path=~/.xpack-dev-tools # For all OS +api_build_tools_url=https://api.github.com/repos/xpack-dev-tools/windows-build-tools-xpack/releases +api_toolchain_url=https://api.github.com/repos/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases + +Extract() { + archive="$1" + + if echo "$archive" | grep -E -- ".zip$" >/dev/null 2>&1; then + unzip -o "$archive" + fi + + if echo "$archive" | grep -E -- ".tar.gz$" >/dev/null 2>&1; then + tar xvf "$archive" + fi +} + +# Usage: Install [api_url] [version] [file_ending] +Install() { + api_url="$1" + version="$2" + file_ending="$3" + + install_folder="xpack-"$(echo "$api_url" | cut -d '/' -f6 | sed "s/xpack/$version/") + # echo "Install folder: $install_folder" + + if [ -d "$install_path/$install_folder" ]; then + echo "Use: $install_folder" + return + fi + + url=$(curl --ssl-no-revoke -s -L "$api_url" | grep -- "browser_download_url" | grep -- "$version" | grep -- "$file_ending\"" | cut -d '"' -f4) + # echo "Download URL: $url" + archive=$(basename "$url") + # echo "Archive: $archive" + + mkdir -p "$install_path" + cd "$install_path" || exit 1 + + curl --ssl-no-revoke -L -O "$url" + Extract "$archive" + rm "$archive" +} + +# Windows +if uname | grep -- "MINGW64" >/dev/null 2>&1; then + Install "$api_build_tools_url" "$build_tools_version" "win32-x64.zip" + Install "$api_toolchain_url" "$toolchain_version" "win32-x64.zip" + exit +fi + +# Linux +if uname | grep -- "Linux" >/dev/null 2>&1; then + if uname -a | grep -- "x86_64" >/dev/null 2>&1; then + Install "$api_toolchain_url" "$toolchain_version" "linux-x64.tar.gz" + elif uname -a | grep -- "aarch64" >/dev/null 2>&1; then + Install "$api_toolchain_url" "$toolchain_version" "linux-arm64.tar.gz" + elif uname -a | grep -- "arm" >/dev/null 2>&1; then + Install "$api_toolchain_url" "$toolchain_version" "linux-arm.tar.gz" + else + echo "Unknown Linux architecture"; exit 1 + fi + if ( ! xxd --version > /dev/null 2>&1 ) || ( ! srec_cat --version > /dev/null 2>&1 ); then + sudo apt update + fi + if ! xxd --version > /dev/null 2>&1; then + sudo apt install -y xxd + else + echo "Use: xxd" + fi + if ! srec_cat --version > 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> $OUTFILE +#ifndef __VERSION_H_ +#define __VERSION_H_ + +// Данный файл обновляется автоматически из скрипта version.sh + +// Хеш коммита в репозитории GIT. +#define GIT_BUILD $git_build + +// Дата компиляции, YYMMDD, всё в bcd. +#define BUILD_DATE $date + +// Версия CAN-прошивки. +#define CAN_FW_VERSION 1 + +// Версия из GIT. +#define GIT_VERSION "$version" + +#endif /* __VERSION_H_ */ +--- diff --git a/sys/zdotdir/.gitignore b/sys/zdotdir/.gitignore new file mode 100644 index 0000000..ee1b1ed --- /dev/null +++ b/sys/zdotdir/.gitignore @@ -0,0 +1,3 @@ +* +!.gitignore +!.zshrc diff --git a/sys/zdotdir/.zshrc b/sys/zdotdir/.zshrc new file mode 100644 index 0000000..ca8d046 --- /dev/null +++ b/sys/zdotdir/.zshrc @@ -0,0 +1,6 @@ +# This script should be sourced, not executed. + +unset ZDOTDIR + +. ~/.zshrc +. sys/export.zsh

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